Change in coreboot[master]: soc/{amd, intel}: Make use of common enable_tseg_cache() API
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35025 )
Change subject: soc/{amd, intel}: Make use of common enable_tseg_cache() API ......................................................................
soc/{amd, intel}: Make use of common enable_tseg_cache() API
This patch removes dedicated function call to make TSEG region cache from soc and refers to enable_tseg_cache().
Change-Id: I18a032b43a2093c8ae86735c119d8dfee40570b1 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c 5 files changed, 10 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/35025/1
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 4f18b42..a41314d 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -44,8 +44,6 @@ { struct postcar_frame pcf; uintptr_t top_of_ram; - uintptr_t smm_base; - size_t smm_size; int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3();
console_init(); @@ -87,15 +85,8 @@ /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
- /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); + /* Cache the TSEG region. */ + enable_tseg_cache(&pcf);
post_code(0x45); run_postcar_phase(&pcf); diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 0d65ef6..09563bb 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -85,8 +85,6 @@ { struct postcar_frame pcf; uintptr_t top_of_ram; - uintptr_t smm_base; - size_t smm_size; msr_t base, mask; msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT; @@ -172,15 +170,8 @@ /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
- /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); + /* Cache the TSEG region. */ + enable_tseg_cache(&pcf);
post_code(0x45); run_postcar_phase(&pcf); diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 1464d2c..ba86a43 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -246,15 +246,8 @@ /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
- /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); + /* Cache the TSEG region. */ + enable_tseg_cache(&pcf);
run_postcar_phase(&pcf); } diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 9c41486..af65d38 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -142,8 +142,6 @@
struct postcar_frame pcf; uintptr_t top_of_ram; - uintptr_t smm_base; - size_t smm_size;
console_init();
@@ -182,8 +180,8 @@ * region for other purposes. */ if (CONFIG(HAVE_SMI_HANDLER)) { - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); + /* Cache the TSEG region. */ + enable_tseg_cache(&pcf); }
run_postcar_phase(&pcf); diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 8b5cd18..1d925b3 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -174,19 +174,8 @@ postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
if (CONFIG(HAVE_SMI_HANDLER)) { - uintptr_t smm_base; - size_t smm_size; - - /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, smm_base, smm_size, - MTRR_TYPE_WRBACK); + /* Cache the TSEG region. */ + enable_tseg_cache(&pcf); }
/* Cache the ROM as WP just below 4GiB. */
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35025 )
Change subject: soc/{amd, intel}: Make use of common enable_tseg_cache() API ......................................................................
Patch Set 1:
Subrata, you realise this is conflicting CB:34893 which you previously said is something Intel wants (and you still have not otherwise reviewed). Also, all work on x86-smm-tseg smm_subregion() will just be slowed down if this is merged.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35025 )
Change subject: soc/{amd, intel}: Make use of common enable_tseg_cache() API ......................................................................
Patch Set 1:
Patch Set 1:
Subrata, you realise this is conflicting CB:34893
CB:34893 is supposed to refactoring code to fit into common romstage.c file if i understood that correctly.
which you previously said is something Intel wants (and you still have not otherwise reviewed).
I mean to say that "Use common romstage code" i like and its too far to reach at that stage using this patch alone. i really wish to maintain exact call sequences common between small cores and big cores and then forward those call into common IP blocks, which might need deep study on entire code that touches some IP initialization sequence and define common path. Not by just making mainboard_romstage_entry()/fill_postcar_frame() name change alone. We are currently working on study path and hopefully get back as and when we have some data ready.
Also, all work on x86-smm-tseg smm_subregion() will just be slowed down if this is merged.
This CB:34995/CB:35025/CB:35026 supposed to address below comments isn't it?
Aaron Durbin Patch Set 4:
Patch Set 4:
Patch Set 4:
I like the idea of adding smm region as WB to the postar mtrr solution. A common API for doing that is helpful . To do it automatically we can add a Kconfig and do this conditional call in run_postcar_phase() or just make the appropriate call in the appropriate romstage.c file.
Got your point, we can create a common API and call that API from run_postcar_phase() or romstage.c but do you think we need any dedicated kconfig when we have TSEG_STAGE_CACHE. My concern is that how do SoC user know if they have to enable TSEG caching as well via another kconfig. I thought it should automatically cache TSEG region but there might be one catch by marking that region as WB as we already learn the WB implication. I guess you are advocating new kconfig just for WB purpose ?
That or just put in calls at the proper places. e.g. replace the smm_region()/postcar_frame_add_mtrr() sequence in apollolake with the correct call. We can follow up with patches which reduce the call sequences from the various code bases with more shared code that could be driven by Kconfigs.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35025 )
Change subject: soc/{amd, intel}: Make use of common enable_tseg_cache() API ......................................................................
Patch Set 1:
Patch Set 1:
Patch Set 1:
Subrata, you realise this is conflicting CB:34893
CB:34893 is supposed to refactoring code to fit into common romstage.c file if i understood that correctly.
And together with CB:34894 we want to consistently have any postcar_frame creations across all platforms dealt with in a file called memmap.c that is unconditionally built for romstage, postcar and ramstage. This makes it easier to review and apply fixes for MTRR alignment and gives you one common point in cpu/intel/car/romstage.c where to enable TSEG cache. Or, use the already existing postcar_frame_add_common_mtrrs().
A lot of these decisions about API depends on whether Aaron or Furguain will accept the use of set_var_mtrr() late in romstage. And whether 'cbmem -t' shows any significant performance boost with your changes. TSEG WB 7ms was a 90% enhancement for memcpy() in stage cache, so it will be accepted in one form or other.
Also, as you don't have stack guard checking in place for intel/cannonlake, I believe your POSTCAR_STAGE=n ipmlementation currently smashes the BSP stack, overwrites VBOOT2_WORK and VBOOT2_TPM_LOG during run_ramstage(). See CB:34882. Just one more reason I think your effort should be on getting CB:34893 and CB:34894 reviewed.
Hello Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Vanny E, build bot (Jenkins), Furquan Shaikh, David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35025
to look at the new patch set (#2).
Change subject: soc/{amd, intel}: Make use of common enable_tseg_cache() API ......................................................................
soc/{amd, intel}: Make use of common enable_tseg_cache() API
This patch removes dedicated function call to make TSEG region cache from soc and refers to enable_tseg_cache().
Change-Id: I18a032b43a2093c8ae86735c119d8dfee40570b1 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c 5 files changed, 11 insertions(+), 50 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/35025/2
Hello Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Vanny E, build bot (Jenkins), Furquan Shaikh, David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35025
to look at the new patch set (#3).
Change subject: soc/{amd, intel}: Make use of common enable_tseg_cache() API ......................................................................
soc/{amd, intel}: Make use of common enable_tseg_cache() API
This patch removes dedicated function call to make TSEG region cache from soc and refers to enable_tseg_cache().
Change-Id: I18a032b43a2093c8ae86735c119d8dfee40570b1 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/skylake/memmap.c 5 files changed, 10 insertions(+), 55 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/35025/3
Hello Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Vanny E, build bot (Jenkins), Furquan Shaikh, David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35025
to look at the new patch set (#4).
Change subject: soc/{amd, intel}: Make use of common enable_tseg_cache() API ......................................................................
soc/{amd, intel}: Make use of common enable_tseg_cache() API
This patch removes dedicated function call to make TSEG region cache from soc and refers to enable_tseg_cache().
BUG=b:140008206
Change-Id: I18a032b43a2093c8ae86735c119d8dfee40570b1 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/skylake/memmap.c 5 files changed, 10 insertions(+), 55 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/35025/4
Subrata Banik has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/35025 )
Change subject: soc/{amd, intel}: Make use of common enable_tseg_cache() API ......................................................................
Abandoned
Subrata Banik has restored this change. ( https://review.coreboot.org/c/coreboot/+/35025 )
Change subject: soc/{amd, intel}: Make use of common enable_tseg_cache() API ......................................................................
Restored
Hello Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Vanny E, build bot (Jenkins), Furquan Shaikh, David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35025
to look at the new patch set (#5).
Change subject: soc/{amd, intel}: Make use of common enable_tseg_cache() API ......................................................................
soc/{amd, intel}: Make use of common enable_tseg_cache() API
This patch removes dedicated function call to make TSEG region cache from soc and refers to enable_tseg_cache().
BUG=b:140008206
Change-Id: I18a032b43a2093c8ae86735c119d8dfee40570b1 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/skylake/memmap.c 5 files changed, 15 insertions(+), 55 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/35025/5
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35025 )
Change subject: soc/{amd, intel}: Make use of common enable_tseg_cache() API ......................................................................
Patch Set 5: Code-Review+2
Hello Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Vanny E, build bot (Jenkins), Furquan Shaikh, David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35025
to look at the new patch set (#6).
Change subject: soc/{amd, intel}: Make use of common postcar_enable_tseg_cache() API ......................................................................
soc/{amd, intel}: Make use of common postcar_enable_tseg_cache() API
This patch removes dedicated function call to make TSEG region cache from soc and refers to postcar_enable_tseg_cache().
BUG=b:140008206
Change-Id: I18a032b43a2093c8ae86735c119d8dfee40570b1 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/skylake/memmap.c 5 files changed, 15 insertions(+), 55 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/35025/6
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35025 )
Change subject: soc/{amd, intel}: Make use of common postcar_enable_tseg_cache() API ......................................................................
Patch Set 6: Code-Review+2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35025 )
Change subject: soc/{amd, intel}: Make use of common postcar_enable_tseg_cache() API ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35025/6/src/soc/amd/picasso/romstag... File src/soc/amd/picasso/romstage.c:
https://review.coreboot.org/c/coreboot/+/35025/6/src/soc/amd/picasso/romstag... PS6, Line 89: if (CONFIG(SMM_TSEG)) Now that the call is in platform code, the conditional is unnecessary. In common code it would have been necessary to have it to handle AGESA (POSTCAR_STAGE=Y, SMM_ASEG=y) cases where we do not implement smm_region().
Hello Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Vanny E, build bot (Jenkins), Furquan Shaikh, David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35025
to look at the new patch set (#7).
Change subject: soc/{amd, intel}: Make use of common postcar_enable_tseg_cache() API ......................................................................
soc/{amd, intel}: Make use of common postcar_enable_tseg_cache() API
This patch removes dedicated function call to make TSEG region cache from soc and refers to postcar_enable_tseg_cache().
BUG=b:140008206
Change-Id: I18a032b43a2093c8ae86735c119d8dfee40570b1 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/skylake/memmap.c 5 files changed, 10 insertions(+), 55 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/35025/7
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35025 )
Change subject: soc/{amd, intel}: Make use of common postcar_enable_tseg_cache() API ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35025/6/src/soc/amd/picasso/romstag... File src/soc/amd/picasso/romstage.c:
https://review.coreboot.org/c/coreboot/+/35025/6/src/soc/amd/picasso/romstag... PS6, Line 89: if (CONFIG(SMM_TSEG))
Now that the call is in platform code, the conditional is unnecessary. […]
Done
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35025 )
Change subject: soc/{amd, intel}: Make use of common postcar_enable_tseg_cache() API ......................................................................
Patch Set 7: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/35025/6/src/soc/amd/picasso/romstag... File src/soc/amd/picasso/romstage.c:
https://review.coreboot.org/c/coreboot/+/35025/6/src/soc/amd/picasso/romstag... PS6, Line 89: if (CONFIG(SMM_TSEG))
Done
Well, that is true assuming smm_region() does the correct thing if someone flips off SMM_TSEG. Otherwise it requires two touch points.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35025 )
Change subject: soc/{amd, intel}: Make use of common postcar_enable_tseg_cache() API ......................................................................
Patch Set 7: Code-Review+2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35025 )
Change subject: soc/{amd, intel}: Make use of common postcar_enable_tseg_cache() API ......................................................................
Patch Set 7: Code-Review+2
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35025 )
Change subject: soc/{amd, intel}: Make use of common postcar_enable_tseg_cache() API ......................................................................
soc/{amd, intel}: Make use of common postcar_enable_tseg_cache() API
This patch removes dedicated function call to make TSEG region cache from soc and refers to postcar_enable_tseg_cache().
BUG=b:140008206
Change-Id: I18a032b43a2093c8ae86735c119d8dfee40570b1 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35025 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/skylake/memmap.c 5 files changed, 10 insertions(+), 55 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Aaron Durbin: Looks good to me, approved Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 4f18b42..9882d91 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -44,8 +44,6 @@ { struct postcar_frame pcf; uintptr_t top_of_ram; - uintptr_t smm_base; - size_t smm_size; int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3();
console_init(); @@ -87,15 +85,8 @@ /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
- /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); + /* Cache the TSEG region */ + postcar_enable_tseg_cache(&pcf);
post_code(0x45); run_postcar_phase(&pcf); diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 0d65ef6..4032d3f 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -85,8 +85,6 @@ { struct postcar_frame pcf; uintptr_t top_of_ram; - uintptr_t smm_base; - size_t smm_size; msr_t base, mask; msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT; @@ -172,15 +170,8 @@ /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
- /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); + /* Cache the TSEG region */ + postcar_enable_tseg_cache(&pcf);
post_code(0x45); run_postcar_phase(&pcf); diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index bda43bb..905fa64 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -53,8 +53,6 @@ void fill_postcar_frame(struct postcar_frame *pcf) { uintptr_t top_of_ram; - uintptr_t smm_base; - size_t smm_size;
/* * We need to make sure ramstage will be run cached. At this point exact @@ -67,13 +65,6 @@ postcar_frame_add_mtrr(pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK);
- /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); + /* Cache the TSEG region */ + postcar_enable_tseg_cache(pcf); } diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index f7b2e07..9f788dd 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -81,8 +81,6 @@ void fill_postcar_frame(struct postcar_frame *pcf) { uintptr_t top_of_ram; - uintptr_t smm_base; - size_t smm_size;
/* * We need to make sure ramstage will be run cached. At this point exact @@ -93,13 +91,6 @@ postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK);
- /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); + /* Cache the TSEG region */ + postcar_enable_tseg_cache(pcf); } diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 4c3c58a..29f2517 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -296,8 +296,6 @@ void fill_postcar_frame(struct postcar_frame *pcf) { uintptr_t top_of_ram; - uintptr_t smm_base; - size_t smm_size;
/* * We need to make sure ramstage will be run cached. At this @@ -310,14 +308,7 @@ top_of_ram -= 16*MiB; postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
- /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); + /* Cache the TSEG region */ + postcar_enable_tseg_cache(pcf); } #endif
-
Aaron Durbin (Code Review) -
Furquan Shaikh (Code Review)
-
Kyösti Mälkki (Code Review)
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Subrata Banik (Code Review)