Change in coreboot[master]: soc/amd/stoneyridge/romstage.c: Fix AGESA warning

[Richard Spiegel (Code Review)]

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/23786

Change subject: soc/amd/stoneyridge/romstage.c: Fix AGESA warning
......................................................................

soc/amd/stoneyridge/romstage.c: Fix AGESA warning

AmdInitPost returns AGESA_WARNING. This is because AGESA by default
enables bank interleaving, while the HW does not meet the requirements
for it. After some investigation, it was found that AGESA was really
checking rank.

Using the new rank function, disable bank interleave if the number of
ranks is odd.

BUG=b:73118857
TEST= Build and run kahlee. Search for "agesawrapper_amdinitpost()
returned AGESA_SUCCESS".

Change-Id: Id8a2a3bc927f87e91d30971b512fac12230aaad7
Signed-off-by: Richard Spiegel 
---
M src/soc/amd/stoneyridge/romstage.c
1 file changed, 3 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/23786/1

diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 351a266..2488ef9 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -176,7 +176,9 @@

cfg = dev->chip_info;
    uint8_t ranks = get_total_ranks(cfg);
-	printk(BIOS_SPEW, "Ranks %d\n", ranks);
+	/* If the number of ranks is odd, disable interleaving */
+	if (ranks & 1)
+		PostParams->MemConfig.EnableBankIntlv = FALSE;

PostParams->MemConfig.EnableMemClr = cfg->dram_clear_on_reset;