Hello Michał Żygowski,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/37440
to review the following change.
Change subject: AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK ......................................................................
AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK
Change-Id: I507ac6d483d9854852d6d01f10544c450b8d33cc Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/drivers/amd/agesa/Makefile.inc M src/drivers/amd/agesa/bootblock.c M src/drivers/amd/agesa/romstage.c M src/northbridge/amd/agesa/family14/Makefile.inc M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/agesa/hudson/Makefile.inc M src/southbridge/amd/agesa/hudson/bootblock.c M src/southbridge/amd/cimx/sb800/Makefile.inc M src/southbridge/amd/cimx/sb800/bootblock.c M src/southbridge/amd/pi/hudson/Kconfig M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/bootblock.c 12 files changed, 19 insertions(+), 100 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/37440/1
diff --git a/src/drivers/amd/agesa/Makefile.inc b/src/drivers/amd/agesa/Makefile.inc index 3c3c4fc..4536fc9 100644 --- a/src/drivers/amd/agesa/Makefile.inc +++ b/src/drivers/amd/agesa/Makefile.inc @@ -19,12 +19,8 @@
ramstage-y += state_machine.c
-ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) bootblock-y += bootblock.c bootblock-y += cache_as_ram.S -else -cpu_incs-y += $(src)/drivers/amd/agesa/cache_as_ram.S -endif
postcar-y += exit_car.S
diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c index 42752bc..e245508 100644 --- a/src/drivers/amd/agesa/bootblock.c +++ b/src/drivers/amd/agesa/bootblock.c @@ -45,6 +45,11 @@ CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_WRBACK); }
+void bootblock_soc_early_init(void) +{ + bootblock_early_southbridge_init(); +} + asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { init_mmio(); diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 684fa66..82450f4 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -15,7 +15,6 @@ #include <arch/acpi.h> #include <arch/cpu.h> #include <arch/romstage.h> -#include <bootblock_common.h> #include <cbmem.h> #include <console/console.h> #include <halt.h> @@ -53,16 +52,10 @@ u8 initial_apic_id = (u8) (cpuid_ebx(1) >> 24); int cbmem_initted = 0;
- /* Enable PCI MMIO configuration. */ - if (CONFIG(ROMCC_BOOTBLOCK)) - amd_initmmio(); - fill_sysinfo(cb);
if (initial_apic_id == 0) {
- if (CONFIG(ROMCC_BOOTBLOCK)) - timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE);
platform_once(cb); @@ -73,8 +66,7 @@ printk(BIOS_DEBUG, "APIC %02d: CPU Family_Model = %08x\n", initial_apic_id, cpuid_eax(1));
- if (!CONFIG(ROMCC_BOOTBLOCK)) - set_ap_entry_ptr(ap_romstage_main); + set_ap_entry_ptr(ap_romstage_main);
agesa_execute_state(cb, AMD_INIT_RESET);
@@ -115,10 +107,6 @@ struct sysinfo romstage_state; struct sysinfo *cb = &romstage_state;
- /* Enable PCI MMIO configuration. */ - if (CONFIG(ROMCC_BOOTBLOCK)) - amd_initmmio(); - fill_sysinfo(cb);
agesa_execute_state(cb, AMD_INIT_RESET); @@ -129,22 +117,7 @@ halt(); }
-#if CONFIG(ROMCC_BOOTBLOCK) -/* This wrapper enables easy transition away from ROMCC_BOOTBLOCK - * keeping changes in cache_as_ram.S easy to manage. - */ -asmlinkage void bootblock_c_entry(uint64_t base_timestamp) -{ - romstage_main(); -} - -asmlinkage void ap_bootblock_c_entry(void) -{ - ap_romstage_main(); -} -#else asmlinkage void car_stage_entry(void) { romstage_main(); } -#endif diff --git a/src/northbridge/amd/agesa/family14/Makefile.inc b/src/northbridge/amd/agesa/family14/Makefile.inc index aad7acc..dd9ba58 100644 --- a/src/northbridge/amd/agesa/family14/Makefile.inc +++ b/src/northbridge/amd/agesa/family14/Makefile.inc @@ -13,9 +13,7 @@ # GNU General Public License for more details. #
-ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) bootblock-y += bootblock.c -endif
romstage-y += dimmSpd.c
diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 93db1a9..e56a493 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -31,10 +31,6 @@ select SOC_AMD_COMMON_BLOCK select SOC_AMD_COMMON_BLOCK_ACPIMMIO
-config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/agesa/hudson/bootblock.c" - config EHCI_BAR hex default 0xfef00000 diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 5c92128..34c7518 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -17,11 +17,9 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c
-ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) bootblock-y += bootblock.c bootblock-y += early_setup.c bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c -endif
romstage-y += enable_usbdebug.c ramstage-y += enable_usbdebug.c diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index 97e8803..bef87e0 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -14,7 +14,10 @@ */
#include <stdint.h> +#include <bootblock_common.h> +#include <amdblocks/acpimmio.h> #include <device/pci_ops.h> +#include <southbridge/amd/agesa/hudson/hudson.h>
/* * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. @@ -56,24 +59,12 @@ pci_io_write_config16(dev, 0x6e, 0xffff); }
-static void bootblock_southbridge_init(void) -{ - hudson_enable_rom(); -} - - -#if !CONFIG(ROMCC_BOOTBLOCK) - -#include <bootblock_common.h> -#include <amdblocks/acpimmio.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -void bootblock_soc_early_init(void) +void bootblock_early_southbridge_init(void) { pci_devfn_t dev; u32 data;
- bootblock_southbridge_init(); + hudson_enable_rom(); hudson_lpc_decode(); enable_acpimmio_decode_pm24();
@@ -89,7 +80,6 @@ * Enable decoding of legacy TPM addresses: IO addresses 0x7f- * 0x7e and 0xef-0xee. */ - data = pci_read_config32(dev, LPC_TRUSTED_PLATFORM_MODULE); data |= TPM_12_EN | TPM_LEGACY_EN; pci_write_config32(dev, LPC_TRUSTED_PLATFORM_MODULE, data); @@ -104,4 +94,3 @@ */ pm_write8(0xd2, 0); } -#endif diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index ccb3a2a..8e27b34 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -16,9 +16,7 @@
# SB800 Platform Files
-ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) bootblock-y += bootblock.c -endif
romstage-y += cfg.c romstage-y += early.c diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index b4f03da..0e11db3 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -13,7 +13,8 @@ * GNU General Public License for more details. */
-#include <arch/io.h> +#include <amdblocks/acpimmio.h> +#include <bootblock_common.h> #include <device/pci_ops.h>
static void enable_rom(void) @@ -79,17 +80,6 @@ pci_io_write_config32(dev, 0xa0, save); }
-static void enable_acpimmio_decode_pm24(void) -{ - u8 reg8; - - outb(0x24, 0xCD6); - reg8 = inb(0xCD7); - reg8 |= 1; - reg8 &= ~(1 << 1); - outb(reg8, 0xCD7); -} - static void enable_clocks(void) { u32 reg32; @@ -109,7 +99,7 @@ *acpi_mmio = reg32; }
-static void bootblock_southbridge_init(void) +void bootblock_early_southbridge_init(void) { /* Setup the ROM access for 2M */ enable_rom(); @@ -120,12 +110,3 @@ enable_acpimmio_decode_pm24(); enable_clocks(); } - -#if !CONFIG(ROMCC_BOOTBLOCK) -#include <bootblock_common.h> - -void bootblock_soc_early_init(void) -{ - bootblock_southbridge_init(); -} -#endif diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 01f3937..ea37e3e 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -34,10 +34,6 @@ select SOC_AMD_COMMON_BLOCK select SOC_AMD_COMMON_BLOCK_ACPIMMIO
-config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/pi/hudson/bootblock.c" - config EHCI_BAR hex default 0xfef00000 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 615fc04..738e0be 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -28,11 +28,9 @@ # #*****************************************************************************
-ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) bootblock-y += bootblock.c bootblock-y += early_setup.c bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c -endif
romstage-y += early_setup.c romstage-y += enable_usbdebug.c diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index e9a9d33..a8fcaac 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -14,7 +14,10 @@ */
#include <stdint.h> +#include <bootblock_common.h> +#include <amdblocks/acpimmio.h> #include <device/pci_ops.h> +#include <southbridge/amd/pi/hudson/hudson.h>
/* * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. @@ -56,23 +59,12 @@ pci_io_write_config16(dev, 0x6e, 0xffff); }
-static void bootblock_southbridge_init(void) -{ - hudson_enable_rom(); -} - -#if !CONFIG(ROMCC_BOOTBLOCK) - -#include <bootblock_common.h> -#include <amdblocks/acpimmio.h> -#include <southbridge/amd/pi/hudson/hudson.h> - -void bootblock_soc_early_init(void) +void bootblock_early_southbridge_init(void) { pci_devfn_t dev; u32 data;
- bootblock_southbridge_init(); + hudson_enable_rom(); hudson_lpc_decode(); if (CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)) enable_acpimmio_decode_pm24(); @@ -106,4 +98,3 @@ */ pm_write8(0xd2, 0); } -#endif
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37440 )
Change subject: AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK ......................................................................
Patch Set 1: Code-Review+2
Michał Żygowski has uploaded a new patch set (#3) to the change originally created by Kyösti Mälkki. ( https://review.coreboot.org/c/coreboot/+/37440 )
Change subject: AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK ......................................................................
AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK
Change-Id: I507ac6d483d9854852d6d01f10544c450b8d33cc Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/drivers/amd/agesa/Makefile.inc M src/drivers/amd/agesa/bootblock.c M src/drivers/amd/agesa/romstage.c M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/agesa/hudson/Makefile.inc M src/southbridge/amd/agesa/hudson/bootblock.c M src/southbridge/amd/cimx/sb800/Makefile.inc M src/southbridge/amd/cimx/sb800/bootblock.c M src/southbridge/amd/pi/hudson/Kconfig M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/bootblock.c 11 files changed, 19 insertions(+), 98 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/37440/3
Hello Arthur Heymans, build bot (Jenkins), Patrick Georgi, Martin Roth, Michał Żygowski,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37440
to look at the new patch set (#7).
Change subject: AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK ......................................................................
AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK
Change-Id: I507ac6d483d9854852d6d01f10544c450b8d33cc Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/amd/agesa/family14/fixme.c M src/cpu/amd/agesa/family15tn/fixme.c M src/cpu/amd/agesa/family16kb/fixme.c M src/cpu/amd/pi/00630F01/fixme.c M src/cpu/amd/pi/00660F01/fixme.c M src/cpu/amd/pi/00730F01/fixme.c M src/drivers/amd/agesa/Makefile.inc M src/drivers/amd/agesa/bootblock.c M src/drivers/amd/agesa/romstage.c M src/northbridge/amd/agesa/agesa_helper.h M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/agesa/hudson/Makefile.inc M src/southbridge/amd/agesa/hudson/bootblock.c M src/southbridge/amd/cimx/sb800/Makefile.inc M src/southbridge/amd/cimx/sb800/bootblock.c M src/southbridge/amd/pi/hudson/Kconfig M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/bootblock.c 18 files changed, 19 insertions(+), 270 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/37440/7
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37440 )
Change subject: AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK ......................................................................
Patch Set 7:
(5 comments)
https://review.coreboot.org/c/coreboot/+/37440/7/src/cpu/amd/agesa/family14/... File src/cpu/amd/agesa/family14/fixme.c:
https://review.coreboot.org/c/coreboot/+/37440/7/src/cpu/amd/agesa/family14/... PS7, Line 88: LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); currently lost with c-env-bootblock
https://review.coreboot.org/c/coreboot/+/37440/7/src/cpu/amd/agesa/family14/... PS7, Line 98: LibAmdMsrWrite(PS_CTL_REG, &MsrReg, &StdHeader); currently lost with c-env-bootblock
https://review.coreboot.org/c/coreboot/+/37440/7/src/cpu/amd/pi/00630F01/fix... File src/cpu/amd/pi/00630F01/fixme.c:
https://review.coreboot.org/c/coreboot/+/37440/7/src/cpu/amd/pi/00630F01/fix... PS7, Line 93: } currently lost with c-env-bootblock
https://review.coreboot.org/c/coreboot/+/37440/7/src/cpu/amd/pi/00660F01/fix... File src/cpu/amd/pi/00660F01/fixme.c:
https://review.coreboot.org/c/coreboot/+/37440/7/src/cpu/amd/pi/00660F01/fix... PS7, Line 99: } currently lost with c-env-bootblock
https://review.coreboot.org/c/coreboot/+/37440/7/src/cpu/amd/pi/00730F01/fix... File src/cpu/amd/pi/00730F01/fixme.c:
https://review.coreboot.org/c/coreboot/+/37440/7/src/cpu/amd/pi/00730F01/fix... PS7, Line 104: } currently lost with c-env-bootblock
Hello Arthur Heymans, build bot (Jenkins), Patrick Georgi, Martin Roth, Michał Żygowski,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37440
to look at the new patch set (#11).
Change subject: AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK ......................................................................
AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK
Change-Id: I507ac6d483d9854852d6d01f10544c450b8d33cc Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/amd/agesa/family14/fixme.c M src/cpu/amd/agesa/family15tn/fixme.c M src/cpu/amd/agesa/family16kb/fixme.c M src/cpu/amd/pi/00630F01/fixme.c M src/cpu/amd/pi/00660F01/fixme.c M src/cpu/amd/pi/00730F01/fixme.c M src/drivers/amd/agesa/Makefile.inc M src/drivers/amd/agesa/bootblock.c M src/drivers/amd/agesa/romstage.c M src/northbridge/amd/agesa/agesa_helper.h M src/northbridge/amd/agesa/family14/state_machine.c M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/agesa/hudson/Makefile.inc M src/southbridge/amd/agesa/hudson/bootblock.c M src/southbridge/amd/cimx/sb800/Makefile.inc M src/southbridge/amd/cimx/sb800/bootblock.c M src/southbridge/amd/pi/hudson/Kconfig M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/bootblock.c 19 files changed, 20 insertions(+), 272 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/37440/11
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37440 )
Change subject: AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK ......................................................................
Patch Set 14: Code-Review+1
Hello HAOUAS Elyes, Arthur Heymans, build bot (Jenkins), Patrick Georgi, Martin Roth, Michał Żygowski,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37440
to look at the new patch set (#15).
Change subject: AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK ......................................................................
AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK
Change-Id: I507ac6d483d9854852d6d01f10544c450b8d33cc Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/amd/agesa/family14/fixme.c M src/cpu/amd/agesa/family15tn/fixme.c M src/cpu/amd/agesa/family16kb/fixme.c M src/cpu/amd/pi/00630F01/fixme.c M src/cpu/amd/pi/00660F01/fixme.c M src/cpu/amd/pi/00730F01/fixme.c M src/drivers/amd/agesa/Makefile.inc M src/drivers/amd/agesa/bootblock.c M src/drivers/amd/agesa/romstage.c M src/northbridge/amd/agesa/agesa_helper.h M src/northbridge/amd/agesa/family14/state_machine.c M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/agesa/hudson/Makefile.inc M src/southbridge/amd/agesa/hudson/bootblock.c M src/southbridge/amd/cimx/sb800/Makefile.inc M src/southbridge/amd/cimx/sb800/bootblock.c M src/southbridge/amd/pi/hudson/Kconfig M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/bootblock.c 19 files changed, 21 insertions(+), 272 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/37440/15
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37440 )
Change subject: AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK ......................................................................
Patch Set 15: Code-Review+1
Hello HAOUAS Elyes, Arthur Heymans, build bot (Jenkins), Patrick Georgi, Martin Roth, Michał Żygowski,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37440
to look at the new patch set (#16).
Change subject: AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK ......................................................................
AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK
Change-Id: I507ac6d483d9854852d6d01f10544c450b8d33cc Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/amd/agesa/family14/fixme.c M src/cpu/amd/agesa/family15tn/fixme.c M src/cpu/amd/agesa/family16kb/fixme.c M src/cpu/amd/pi/00630F01/fixme.c M src/cpu/amd/pi/00660F01/fixme.c M src/cpu/amd/pi/00730F01/fixme.c M src/drivers/amd/agesa/Makefile.inc M src/drivers/amd/agesa/bootblock.c M src/drivers/amd/agesa/romstage.c M src/northbridge/amd/agesa/agesa_helper.h M src/northbridge/amd/agesa/family14/state_machine.c M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/agesa/hudson/Makefile.inc M src/southbridge/amd/agesa/hudson/bootblock.c M src/southbridge/amd/cimx/sb800/Makefile.inc M src/southbridge/amd/cimx/sb800/bootblock.c M src/southbridge/amd/pi/hudson/Kconfig M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/bootblock.c 19 files changed, 21 insertions(+), 240 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/37440/16
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37440 )
Change subject: AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK ......................................................................
Patch Set 16:
(5 comments)
https://review.coreboot.org/c/coreboot/+/37440/7/src/cpu/amd/agesa/family14/... File src/cpu/amd/agesa/family14/fixme.c:
https://review.coreboot.org/c/coreboot/+/37440/7/src/cpu/amd/agesa/family14/... PS7, Line 88: LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
currently lost with c-env-bootblock
Done
https://review.coreboot.org/c/coreboot/+/37440/7/src/cpu/amd/agesa/family14/... PS7, Line 98: LibAmdMsrWrite(PS_CTL_REG, &MsrReg, &StdHeader);
currently lost with c-env-bootblock
Done
https://review.coreboot.org/c/coreboot/+/37440/7/src/cpu/amd/pi/00630F01/fix... File src/cpu/amd/pi/00630F01/fixme.c:
https://review.coreboot.org/c/coreboot/+/37440/7/src/cpu/amd/pi/00630F01/fix... PS7, Line 93: }
currently lost with c-env-bootblock
Done
https://review.coreboot.org/c/coreboot/+/37440/7/src/cpu/amd/pi/00660F01/fix... File src/cpu/amd/pi/00660F01/fixme.c:
https://review.coreboot.org/c/coreboot/+/37440/7/src/cpu/amd/pi/00660F01/fix... PS7, Line 99: }
currently lost with c-env-bootblock
Done
https://review.coreboot.org/c/coreboot/+/37440/7/src/cpu/amd/pi/00730F01/fix... File src/cpu/amd/pi/00730F01/fixme.c:
https://review.coreboot.org/c/coreboot/+/37440/7/src/cpu/amd/pi/00730F01/fix... PS7, Line 104: }
currently lost with c-env-bootblock
Done
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37440 )
Change subject: AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK ......................................................................
Patch Set 16: Code-Review+1
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37440 )
Change subject: AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK ......................................................................
Patch Set 16: Code-Review+1
Don't know why the merge conflict
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37440 )
Change subject: AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK ......................................................................
Patch Set 16:
Patch Set 16: Code-Review+1
Don't know why the merge conflict
maybe because of the 'relation chain'
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37440 )
Change subject: AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK ......................................................................
Patch Set 16: Code-Review+1
I would rebase this once dependent changes get merged, to avoid potential issues.
Hello HAOUAS Elyes, Angel Pons, Arthur Heymans, build bot (Jenkins), Michał Żygowski, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37440
to look at the new patch set (#18).
Change subject: AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK ......................................................................
AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK
Change-Id: I507ac6d483d9854852d6d01f10544c450b8d33cc Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/amd/agesa/family14/fixme.c M src/cpu/amd/agesa/family15tn/fixme.c M src/cpu/amd/agesa/family16kb/fixme.c M src/cpu/amd/pi/00630F01/fixme.c M src/cpu/amd/pi/00660F01/fixme.c M src/cpu/amd/pi/00730F01/fixme.c M src/drivers/amd/agesa/Makefile.inc M src/drivers/amd/agesa/bootblock.c M src/drivers/amd/agesa/romstage.c M src/northbridge/amd/agesa/agesa_helper.h M src/northbridge/amd/agesa/family14/state_machine.c M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/agesa/hudson/Makefile.inc M src/southbridge/amd/agesa/hudson/bootblock.c M src/southbridge/amd/cimx/sb800/Makefile.inc M src/southbridge/amd/cimx/sb800/bootblock.c M src/southbridge/amd/pi/hudson/Kconfig M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/bootblock.c 19 files changed, 21 insertions(+), 240 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/37440/18
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37440 )
Change subject: AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK ......................................................................
Patch Set 18: Code-Review+2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37440 )
Change subject: AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK ......................................................................
Patch Set 18:
Needs some non-author reviews.
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37440 )
Change subject: AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK ......................................................................
Patch Set 19: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37440 )
Change subject: AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK ......................................................................
AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK
Change-Id: I507ac6d483d9854852d6d01f10544c450b8d33cc Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/37440 Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/cpu/amd/agesa/family14/fixme.c M src/cpu/amd/agesa/family15tn/fixme.c M src/cpu/amd/agesa/family16kb/fixme.c M src/cpu/amd/pi/00630F01/fixme.c M src/cpu/amd/pi/00660F01/fixme.c M src/cpu/amd/pi/00730F01/fixme.c M src/drivers/amd/agesa/Makefile.inc M src/drivers/amd/agesa/bootblock.c M src/drivers/amd/agesa/romstage.c M src/northbridge/amd/agesa/agesa_helper.h M src/northbridge/amd/agesa/family14/state_machine.c M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/agesa/hudson/Makefile.inc M src/southbridge/amd/agesa/hudson/bootblock.c M src/southbridge/amd/cimx/sb800/Makefile.inc M src/southbridge/amd/cimx/sb800/bootblock.c M src/southbridge/amd/pi/hudson/Kconfig M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/bootblock.c 19 files changed, 21 insertions(+), 240 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved HAOUAS Elyes: Looks good to me, approved
diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index c9d3039..be7c635 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -61,25 +61,6 @@ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); }
-void amd_initmmio(void) -{ - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | MTRR_TYPE_WRPROT; - LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | MTRR_PHYS_MASK_VALID; - LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); -} - void amd_initenv(void) { AMD_INTERFACE_PARAMS AmdParamStruct; diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c index e92aa9a..03c6503 100644 --- a/src/cpu/amd/agesa/family15tn/fixme.c +++ b/src/cpu/amd/agesa/family15tn/fixme.c @@ -60,22 +60,3 @@ PciData = 0x00000003; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } - -void amd_initmmio(void) -{ - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); -} diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c index 73d0995..260efc2 100644 --- a/src/cpu/amd/agesa/family16kb/fixme.c +++ b/src/cpu/amd/agesa/family16kb/fixme.c @@ -60,22 +60,3 @@ PciData = 0x00000003; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } - -void amd_initmmio(void) -{ - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); -} diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c index d94215a..4699eea 100644 --- a/src/cpu/amd/pi/00630F01/fixme.c +++ b/src/cpu/amd/pi/00630F01/fixme.c @@ -65,24 +65,3 @@ PciData = 0x00000003; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } - -void amd_initmmio(void) -{ - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - * Set the MMIO Configuration Base Address - * and Bus Range onto MMIO configuration base - * Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | - (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); -} diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c index 7d71e2e..1ce7432 100644 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -64,31 +64,3 @@ PciData = 0x00000003; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } - -void amd_initmmio(void) -{ - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* - * Set the MMIO Configuration Base Address and - * Bus Range onto MMIO configuration base - * Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | - (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); - - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); -} diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index 7edd1b8..1ce7432 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -64,36 +64,3 @@ PciData = 0x00000003; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } - -void amd_initmmio(void) -{ - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* - * Set the MMIO Configuration Base Address and - * Bus Range onto MMIO configuration base - * Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | - (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); - - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* PSP */ - //PciData = 0xD; - //PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x8, 0x0, 0x48); - //LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); -} diff --git a/src/drivers/amd/agesa/Makefile.inc b/src/drivers/amd/agesa/Makefile.inc index 3c3c4fc..4536fc9 100644 --- a/src/drivers/amd/agesa/Makefile.inc +++ b/src/drivers/amd/agesa/Makefile.inc @@ -19,12 +19,8 @@
ramstage-y += state_machine.c
-ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) bootblock-y += bootblock.c bootblock-y += cache_as_ram.S -else -cpu_incs-y += $(src)/drivers/amd/agesa/cache_as_ram.S -endif
postcar-y += exit_car.S
diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c index 91fcc6b..7732f27 100644 --- a/src/drivers/amd/agesa/bootblock.c +++ b/src/drivers/amd/agesa/bootblock.c @@ -16,6 +16,7 @@ #include <timestamp.h> #include <amdblocks/amd_pci_mmconf.h> #include <amdblocks/biosram.h> +#include <arch/bootblock.h> #include <cpu/amd/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/lapic.h> @@ -29,6 +30,11 @@ OPTIMAL_CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); }
+void bootblock_soc_early_init(void) +{ + bootblock_early_southbridge_init(); +} + asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { enable_pci_mmconf(); diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index ee4d45e..e8f4da2 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -15,7 +15,6 @@ #include <arch/acpi.h> #include <arch/cpu.h> #include <arch/romstage.h> -#include <bootblock_common.h> #include <cbmem.h> #include <console/console.h> #include <halt.h> @@ -50,16 +49,10 @@ u8 initial_apic_id = (u8) (cpuid_ebx(1) >> 24); int cbmem_initted = 0;
- /* Enable PCI MMIO configuration. */ - if (CONFIG(ROMCC_BOOTBLOCK)) - amd_initmmio(); - fill_sysinfo(cb);
if (initial_apic_id == 0) {
- if (CONFIG(ROMCC_BOOTBLOCK)) - timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE);
board_BeforeAgesa(cb); @@ -70,8 +63,7 @@ printk(BIOS_DEBUG, "APIC %02d: CPU Family_Model = %08x\n", initial_apic_id, cpuid_eax(1));
- if (!CONFIG(ROMCC_BOOTBLOCK)) - set_ap_entry_ptr(ap_romstage_main); + set_ap_entry_ptr(ap_romstage_main);
agesa_execute_state(cb, AMD_INIT_RESET);
@@ -112,10 +104,6 @@ struct sysinfo romstage_state; struct sysinfo *cb = &romstage_state;
- /* Enable PCI MMIO configuration. */ - if (CONFIG(ROMCC_BOOTBLOCK)) - amd_initmmio(); - fill_sysinfo(cb);
agesa_execute_state(cb, AMD_INIT_RESET); @@ -126,22 +114,7 @@ halt(); }
-#if CONFIG(ROMCC_BOOTBLOCK) -/* This wrapper enables easy transition away from ROMCC_BOOTBLOCK - * keeping changes in cache_as_ram.S easy to manage. - */ -asmlinkage void bootblock_c_entry(uint64_t base_timestamp) -{ - romstage_main(); -} - -asmlinkage void ap_bootblock_c_entry(void) -{ - ap_romstage_main(); -} -#else asmlinkage void car_stage_entry(void) { romstage_main(); } -#endif diff --git a/src/northbridge/amd/agesa/agesa_helper.h b/src/northbridge/amd/agesa/agesa_helper.h index dcc3360..a52b069 100644 --- a/src/northbridge/amd/agesa/agesa_helper.h +++ b/src/northbridge/amd/agesa/agesa_helper.h @@ -36,7 +36,6 @@ void *agesawrapper_getlateinitptr (int pick);
void amd_initcpuio(void); -void amd_initmmio(void); void amd_initenv(void);
void *GetHeapBase(void); diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c index 91a8f70..ab96b75 100644 --- a/src/northbridge/amd/agesa/family14/state_machine.c +++ b/src/northbridge/amd/agesa/family14/state_machine.c @@ -32,8 +32,7 @@ if (!boot_cpu()) return;
- if (!CONFIG(ROMCC_BOOTBLOCK)) - sb_Poweron_Init(); + sb_Poweron_Init();
/* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all * would fail later in AmdInitPost(), when DRAM is already configured diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 93db1a9..e56a493 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -31,10 +31,6 @@ select SOC_AMD_COMMON_BLOCK select SOC_AMD_COMMON_BLOCK_ACPIMMIO
-config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/agesa/hudson/bootblock.c" - config EHCI_BAR hex default 0xfef00000 diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index be4ea26..b8eb5b9 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -16,11 +16,9 @@
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
-ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) bootblock-y += bootblock.c bootblock-y += early_setup.c bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c -endif
romstage-y += enable_usbdebug.c ramstage-y += enable_usbdebug.c diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index 4da030b..517b928 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -14,7 +14,10 @@ */
#include <stdint.h> +#include <arch/bootblock.h> +#include <amdblocks/acpimmio.h> #include <device/pci_ops.h> +#include <southbridge/amd/agesa/hudson/hudson.h>
/* * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. @@ -56,24 +59,12 @@ pci_io_write_config16(dev, 0x6e, 0xffff); }
-static void bootblock_southbridge_init(void) -{ - hudson_enable_rom(); -} - - -#if !CONFIG(ROMCC_BOOTBLOCK) - -#include <bootblock_common.h> -#include <amdblocks/acpimmio.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -void bootblock_soc_early_init(void) +void bootblock_early_southbridge_init(void) { pci_devfn_t dev; u32 data;
- bootblock_southbridge_init(); + hudson_enable_rom(); enable_acpimmio_decode_pm24(); hudson_lpc_decode();
@@ -94,7 +85,6 @@ * Enable decoding of legacy TPM addresses: IO addresses 0x7f- * 0x7e and 0xef-0xee. */ - data = pci_read_config32(dev, LPC_TRUSTED_PLATFORM_MODULE); data |= TPM_12_EN | TPM_LEGACY_EN; pci_write_config32(dev, LPC_TRUSTED_PLATFORM_MODULE, data); @@ -109,4 +99,3 @@ */ pm_write8(0xd2, 0); } -#endif diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 5a68d07..2c51648 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -16,9 +16,7 @@
# SB800 Platform Files
-ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) bootblock-y += bootblock.c -endif
romstage-y += cfg.c romstage-y += early.c diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index b4f03da..d42e7ee 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -13,7 +13,8 @@ * GNU General Public License for more details. */
-#include <arch/io.h> +#include <amdblocks/acpimmio.h> +#include <arch/bootblock.h> #include <device/pci_ops.h>
static void enable_rom(void) @@ -79,17 +80,6 @@ pci_io_write_config32(dev, 0xa0, save); }
-static void enable_acpimmio_decode_pm24(void) -{ - u8 reg8; - - outb(0x24, 0xCD6); - reg8 = inb(0xCD7); - reg8 |= 1; - reg8 &= ~(1 << 1); - outb(reg8, 0xCD7); -} - static void enable_clocks(void) { u32 reg32; @@ -109,7 +99,7 @@ *acpi_mmio = reg32; }
-static void bootblock_southbridge_init(void) +void bootblock_early_southbridge_init(void) { /* Setup the ROM access for 2M */ enable_rom(); @@ -120,12 +110,3 @@ enable_acpimmio_decode_pm24(); enable_clocks(); } - -#if !CONFIG(ROMCC_BOOTBLOCK) -#include <bootblock_common.h> - -void bootblock_soc_early_init(void) -{ - bootblock_southbridge_init(); -} -#endif diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 01f3937..ea37e3e 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -34,10 +34,6 @@ select SOC_AMD_COMMON_BLOCK select SOC_AMD_COMMON_BLOCK_ACPIMMIO
-config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/pi/hudson/bootblock.c" - config EHCI_BAR hex default 0xfef00000 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 4aa9bab..9d985e6d 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -28,11 +28,9 @@ # #*****************************************************************************
-ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) bootblock-y += bootblock.c bootblock-y += early_setup.c bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c -endif
romstage-y += early_setup.c romstage-y += enable_usbdebug.c diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index d16aecc..77a4570 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -14,7 +14,10 @@ */
#include <stdint.h> +#include <arch/bootblock.h> +#include <amdblocks/acpimmio.h> #include <device/pci_ops.h> +#include <southbridge/amd/pi/hudson/hudson.h>
/* * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. @@ -56,23 +59,12 @@ pci_io_write_config16(dev, 0x6e, 0xffff); }
-static void bootblock_southbridge_init(void) -{ - hudson_enable_rom(); -} - -#if !CONFIG(ROMCC_BOOTBLOCK) - -#include <bootblock_common.h> -#include <amdblocks/acpimmio.h> -#include <southbridge/amd/pi/hudson/hudson.h> - -void bootblock_soc_early_init(void) +void bootblock_early_southbridge_init(void) { pci_devfn_t dev; u32 data;
- bootblock_southbridge_init(); + hudson_enable_rom(); if (CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)) enable_acpimmio_decode_pm24(); else @@ -111,4 +103,3 @@ */ pm_write8(0xd2, 0); } -#endif
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
HAOUAS Elyes (Code Review)
-
Kyösti Mälkki (Code Review)
-
Michał Żygowski (Code Review)
-
Patrick Georgi (Code Review)