[S] Change in coreboot[master]: soc/intel/alderlake: skip external buses for D-states list

[Eran Mitrani (Code Review)]

Attention is currently required from: Tarun Tuli, Subrata Banik.

Hello Tarun Tuli, Subrata Banik,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/70163

to look at the new patch set (#3).

Change subject: soc/intel/alderlake: skip external buses for D-states list
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soc/intel/alderlake: skip external buses for D-states list

The devices in the list that was introduced in commit
c66ea9857768 ("soc/intel/alderlake: provide a list of D-states to enter
LPM") are all internal. This CL skips the external buses (which caused
the addition of packages to non-existant paths such as
"_SB.PCI0.RP1.MCHC", and warnings from the kernel)

BUG=b:231582182
TEST=Built and tested on anahera by verifying SSDT contents

Change-Id: I3785b2b2af85d96e2e1296b6cfdefcd72080b5fe
Signed-off-by: Eran Mitrani 
---
M src/soc/intel/alderlake/acpi.c
1 file changed, 22 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/70163/3