Hello Tim Chen,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/38458
to review the following change.
Change subject: mainboard/google/puff: update SATA strength ......................................................................
mainboard/google/puff: update SATA strength
Base on SATA SI report to fine tune the strength for port 1.
BRANCH=none BUG=b:147351936 TEST=build and test SATA port works fine.
Change-Id: Ib82b7e5df32b4ce794682781f33c44dfeb6e68bf Signed-off-by: Tim Chen tim-chen@quanta.corp-partner.google.com --- M src/mainboard/google/hatch/variants/puff/overridetree.cb 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/38458/1
diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index e3ccc61..bddc39e 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -122,6 +122,10 @@ # GPIO for SD card detect register "sdcard_cd_gpio" = "vSD3_CD_B"
+ # SATA port 1 Gen3 Strength + register "PchSataHsioTxGen3DeEmphEnable[1]" = "1" + register "PchSataHsioTxGen3DeEmph[1]" = "0x20" + device domain 0 on device pci 14.0 on chip drivers/usb/acpi
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38458 )
Change subject: mainboard/google/puff: update SATA strength ......................................................................
Patch Set 1: Code-Review+2
Jamie Chen has uploaded a new patch set (#2) to the change originally created by Tim Chen. ( https://review.coreboot.org/c/coreboot/+/38458 )
Change subject: mainboard/google/puff: update SATA strength ......................................................................
mainboard/google/puff: update SATA strength
Base on SATA SI report to fine tune the strength for port 1.
BRANCH=none BUG=b:147351936 TEST=build and test SATA port works fine.
Change-Id: Ib82b7e5df32b4ce794682781f33c44dfeb6e68bf Signed-off-by: Tim Chen tim-chen@quanta.corp-partner.google.com --- M src/mainboard/google/hatch/variants/puff/overridetree.cb 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/38458/2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38458 )
Change subject: mainboard/google/puff: update SATA strength ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38458/2/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38458/2/src/mainboard/google/hatch/... PS2, Line 127: register "sata_port[1].TxGen3DeEmph" = "0x20" Add comment what 0x20?
Jamie Chen has uploaded a new patch set (#3) to the change originally created by Tim Chen. ( https://review.coreboot.org/c/coreboot/+/38458 )
Change subject: mainboard/google/puff: update SATA strength ......................................................................
mainboard/google/puff: update SATA strength
Base on SATA SI report to fine tune the strength for port 1.
BRANCH=none BUG=b:147351936 TEST=build and test SATA port works fine.
Change-Id: Ib82b7e5df32b4ce794682781f33c44dfeb6e68bf Signed-off-by: Tim Chen tim-chen@quanta.corp-partner.google.com --- M src/mainboard/google/hatch/variants/puff/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/38458/3
Jamie Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38458 )
Change subject: mainboard/google/puff: update SATA strength ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38458/2/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38458/2/src/mainboard/google/hatch/... PS2, Line 127: register "sata_port[1].TxGen3DeEmph" = "0x20"
Add comment what 0x20?
Done
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38458 )
Change subject: mainboard/google/puff: update SATA strength ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38458 )
Change subject: mainboard/google/puff: update SATA strength ......................................................................
mainboard/google/puff: update SATA strength
Base on SATA SI report to fine tune the strength for port 1.
BRANCH=none BUG=b:147351936 TEST=build and test SATA port works fine.
Change-Id: Ib82b7e5df32b4ce794682781f33c44dfeb6e68bf Signed-off-by: Tim Chen tim-chen@quanta.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38458 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Edward O'Callaghan quasisec@chromium.org --- M src/mainboard/google/hatch/variants/puff/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index 402b98b..2e40ba9 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -171,6 +171,11 @@ # GPIO for SD card detect register "sdcard_cd_gpio" = "vSD3_CD_B"
+ # SATA port 1 Gen3 Strength + # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB + register "sata_port[1].TxGen3DeEmphEnable" = "1" + register "sata_port[1].TxGen3DeEmph" = "0x20" + device domain 0 on device pci 14.0 on chip drivers/usb/acpi
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Edward O'Callaghan (Code Review) -
Jamie Chen (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)
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Tim Chen (Code Review)