Change in coreboot[master]: [DO NOT MERGE] LPT/WPT: WIP unification - coreboot-gerrit

18 Jun 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42520 )
Change subject: [DO NOT MERGE] LPT/WPT: WIP unification
......................................................................
[DO NOT MERGE] LPT/WPT: WIP unification
Change-Id: I62e80c009f8360b1d780db84eeddc6dc1799ee98
Signed-off-by: Angel Pons th3fanbus@gmail.com
---
A src/southbridge/intel/lynxpoint/lpt_nvs.h
A src/southbridge/intel/lynxpoint/nvs.c
M src/southbridge/intel/lynxpoint/nvs.h
M src/southbridge/intel/lynxpoint/serialio.c
M src/southbridge/intel/wildcatpoint/nvs.h
5 files changed, 125 insertions(+), 85 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/42520/1

diff --git a/src/southbridge/intel/lynxpoint/lpt_nvs.h b/src/southbridge/intel/lynxpoint/lpt_nvs.h
new file mode 100644
index 0000000..08d8043
--- /dev/null
+++ b/src/southbridge/intel/lynxpoint/lpt_nvs.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <commonlib/helpers.h>
+#include <stdint.h>
+#include "vendorcode/google/chromeos/gnvs.h"
+
+typedef struct global_nvs_t {
+	/* Miscellaneous */
+	u16	osys; /* 0x00 - Operating System */
+	u8	smif; /* 0x02 - SMI function call ("TRAP") */
+	u8	prm0; /* 0x03 - SMI function call parameter */
+	u8	prm1; /* 0x04 - SMI function call parameter */
+	u8	scif; /* 0x05 - SCI function call (via _L00) */
+	u8	prm2; /* 0x06 - SCI function call parameter */
+	u8	prm3; /* 0x07 - SCI function call parameter */
+	u8	lckf; /* 0x08 - Global Lock function for EC */
+	u8	prm4; /* 0x09 - Lock function parameter */
+	u8	prm5; /* 0x0a - Lock function parameter */
+	u32	p80d; /* 0x0b - Debug port (IO 0x80) value */
+	u8	lids; /* 0x0f - LID state (open = 1) */
+	u8	pwrs; /* 0x10 - Power state (AC = 1) */
+	/* Thermal policy */
+	u8	tlvl; /* 0x11 - Throttle Level Limit */
+	u8	flvl; /* 0x12 - Current FAN Level */
+	u8	tcrt; /* 0x13 - Critical Threshold */
+	u8	tpsv; /* 0x14 - Passive Threshold */
+	u8	tmax; /* 0x15 - CPU Tj_max */
+	u8	f0of; /* 0x16 - FAN 0 OFF Threshold */
+	u8	f0on; /* 0x17 - FAN 0 ON Threshold */
+	u8	f0pw; /* 0x18 - FAN 0 PWM value */
+	u8	f1of; /* 0x19 - FAN 1 OFF Threshold */
+	u8	f1on; /* 0x1a - FAN 1 ON Threshold */
+	u8	f1pw; /* 0x1b - FAN 1 PWM value */
+	u8	f2of; /* 0x1c - FAN 2 OFF Threshold */
+	u8	f2on; /* 0x1d - FAN 2 ON Threshold */
+	u8	f2pw; /* 0x1e - FAN 2 PWM value */
+	u8	f3of; /* 0x1f - FAN 3 OFF Threshold */
+	u8	f3on; /* 0x20 - FAN 3 ON Threshold */
+	u8	f3pw; /* 0x21 - FAN 3 PWM value */
+	u8	f4of; /* 0x22 - FAN 4 OFF Threshold */
+	u8	f4on; /* 0x23 - FAN 4 ON Threshold */
+	u8	f4pw; /* 0x24 - FAN 4 PWM value */
+	u8	tmps; /* 0x25 - Temperature Sensor ID */
+	u8	rsvd3[2];
+	/* Processor Identification */
+	u8	apic; /* 0x28 - APIC enabled */
+	u8	mpen; /* 0x29 - MP capable/enabled */
+	u8	pcp0; /* 0x2a - PDC CPU/CORE 0 */
+	u8	pcp1; /* 0x2b - PDC CPU/CORE 1 */
+	u8	ppcm; /* 0x2c - Max. PPC state */
+	u8      pcnt; /* 0x2d - Processor Count */
+	u8	rsvd4[4];
+	/* Super I/O & CMOS config */
+	u8	natp; /* 0x32 - SIO type */
+	u8	s5u0; /* 0x33 - Enable USB0 in S5 */
+	u8	s5u1; /* 0x34 - Enable USB1 in S5 */
+	u8	s3u0; /* 0x35 - Enable USB0 in S3 */
+	u8	s3u1; /* 0x36 - Enable USB1 in S3 */
+	u8	s33g; /* 0x37 - Enable S3 in 3G */
+	u32	obsolete_cmem; /* 0x38 - CBMEM TOC */
+	/* Integrated Graphics Device */
+	u8	igds; /* 0x3c - IGD state */
+	u8	tlst; /* 0x3d - Display Toggle List Pointer */
+	u8	cadl; /* 0x3e - currently attached devices */
+	u8	padl; /* 0x3f - previously attached devices */
+	u8	rsvd14[27];
+	/* TPM support */
+	u8	tpmp; /* 0x5b - TPM Present */
+	u8	tpme; /* 0x5c - TPM Enable */
+	u8	rsvd5[3];
+	/* LynxPoint Serial IO device BARs */
+	u32	s0b[8]; /* 0x60 - 0x7f - BAR0 */
+	u32	s1b[8]; /* 0x80 - 0x9f - BAR1 */
+	u32	cbmc;   /* 0xa0 - 0xa3 - coreboot memconsole */
+	u8	rsvd6[92];
+
+	/* ChromeOS specific (starts at 0x100)*/
+	chromeos_acpi_t chromeos;
+} __packed global_nvs_t;
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+
+/* Used in SMM to find the ACPI GNVS address */
+global_nvs_t *smm_get_gnvs(void);
+
+void acpi_create_gnvs(global_nvs_t *gnvs);
+
+static inline void gnvs_set_sio_bar0(global_nvs_t *gnvs, int sio_index, u32 bar0_base)
+{
+	gnvs->s0b[sio_index] = bar0_base;
+}
+
+static inline void gnvs_set_sio_bar1(global_nvs_t *gnvs, int sio_index, u32 bar1_base)
+{
+	gnvs->s1b[sio_index] = bar1_base;
+}
diff --git a/src/southbridge/intel/lynxpoint/nvs.c b/src/southbridge/intel/lynxpoint/nvs.c
new file mode 100644
index 0000000..03fc48e
--- /dev/null
+++ b/src/southbridge/intel/lynxpoint/nvs.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <device/pci_ops.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "chip.h"
+#include "iobp.h"
+#include "pch.h"
+#include "nvs.h"
diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h
index b5b6e9f..48af38f 100644
--- a/src/southbridge/intel/lynxpoint/nvs.h
+++ b/src/southbridge/intel/lynxpoint/nvs.h
@@ -1,85 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-#include <commonlib/helpers.h>
-#include <stdint.h>
-#include "vendorcode/google/chromeos/gnvs.h"
-
-typedef struct global_nvs_t {
-	/* Miscellaneous */
-	u16	osys; /* 0x00 - Operating System */
-	u8	smif; /* 0x02 - SMI function call ("TRAP") */
-	u8	prm0; /* 0x03 - SMI function call parameter */
-	u8	prm1; /* 0x04 - SMI function call parameter */
-	u8	scif; /* 0x05 - SCI function call (via _L00) */
-	u8	prm2; /* 0x06 - SCI function call parameter */
-	u8	prm3; /* 0x07 - SCI function call parameter */
-	u8	lckf; /* 0x08 - Global Lock function for EC */
-	u8	prm4; /* 0x09 - Lock function parameter */
-	u8	prm5; /* 0x0a - Lock function parameter */
-	u32	p80d; /* 0x0b - Debug port (IO 0x80) value */
-	u8	lids; /* 0x0f - LID state (open = 1) */
-	u8	pwrs; /* 0x10 - Power state (AC = 1) */
-	/* Thermal policy */
-	u8	tlvl; /* 0x11 - Throttle Level Limit */
-	u8	flvl; /* 0x12 - Current FAN Level */
-	u8	tcrt; /* 0x13 - Critical Threshold */
-	u8	tpsv; /* 0x14 - Passive Threshold */
-	u8	tmax; /* 0x15 - CPU Tj_max */
-	u8	f0of; /* 0x16 - FAN 0 OFF Threshold */
-	u8	f0on; /* 0x17 - FAN 0 ON Threshold */
-	u8	f0pw; /* 0x18 - FAN 0 PWM value */
-	u8	f1of; /* 0x19 - FAN 1 OFF Threshold */
-	u8	f1on; /* 0x1a - FAN 1 ON Threshold */
-	u8	f1pw; /* 0x1b - FAN 1 PWM value */
-	u8	f2of; /* 0x1c - FAN 2 OFF Threshold */
-	u8	f2on; /* 0x1d - FAN 2 ON Threshold */
-	u8	f2pw; /* 0x1e - FAN 2 PWM value */
-	u8	f3of; /* 0x1f - FAN 3 OFF Threshold */
-	u8	f3on; /* 0x20 - FAN 3 ON Threshold */
-	u8	f3pw; /* 0x21 - FAN 3 PWM value */
-	u8	f4of; /* 0x22 - FAN 4 OFF Threshold */
-	u8	f4on; /* 0x23 - FAN 4 ON Threshold */
-	u8	f4pw; /* 0x24 - FAN 4 PWM value */
-	u8	tmps; /* 0x25 - Temperature Sensor ID */
-	u8	rsvd3[2];
-	/* Processor Identification */
-	u8	apic; /* 0x28 - APIC enabled */
-	u8	mpen; /* 0x29 - MP capable/enabled */
-	u8	pcp0; /* 0x2a - PDC CPU/CORE 0 */
-	u8	pcp1; /* 0x2b - PDC CPU/CORE 1 */
-	u8	ppcm; /* 0x2c - Max. PPC state */
-	u8      pcnt; /* 0x2d - Processor Count */
-	u8	rsvd4[4];
-	/* Super I/O & CMOS config */
-	u8	natp; /* 0x32 - SIO type */
-	u8	s5u0; /* 0x33 - Enable USB0 in S5 */
-	u8	s5u1; /* 0x34 - Enable USB1 in S5 */
-	u8	s3u0; /* 0x35 - Enable USB0 in S3 */
-	u8	s3u1; /* 0x36 - Enable USB1 in S3 */
-	u8	s33g; /* 0x37 - Enable S3 in 3G */
-	u32	obsolete_cmem; /* 0x38 - CBMEM TOC */
-	/* Integrated Graphics Device */
-	u8	igds; /* 0x3c - IGD state */
-	u8	tlst; /* 0x3d - Display Toggle List Pointer */
-	u8	cadl; /* 0x3e - currently attached devices */
-	u8	padl; /* 0x3f - previously attached devices */
-	u8	rsvd14[27];
-	/* TPM support */
-	u8	tpmp; /* 0x5b - TPM Present */
-	u8	tpme; /* 0x5c - TPM Enable */
-	u8	rsvd5[3];
-	/* LynxPoint Serial IO device BARs */
-	u32	s0b[8]; /* 0x60 - 0x7f - BAR0 */
-	u32	s1b[8]; /* 0x80 - 0x9f - BAR1 */
-	u32	cbmc;   /* 0xa0 - 0xa3 - coreboot memconsole */
-	u8	rsvd6[92];
-
-	/* ChromeOS specific (starts at 0x100)*/
-	chromeos_acpi_t chromeos;
-} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
-
-/* Used in SMM to find the ACPI GNVS address */
-global_nvs_t *smm_get_gnvs(void);
-
-void acpi_create_gnvs(global_nvs_t * gnvs);
+#if CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT)
+#include <southbridge/intel/lynxpoint/lpt_nvs.h>
+#elif CONFIG(SOUTHBRIDGE_INTEL_WILDCATPOINT)
+#include <southbridge/intel/wildcatpoint/nvs.h>
+#endif
diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c
index 8c2d940..cfa9f21 100644
--- a/src/southbridge/intel/lynxpoint/serialio.c
+++ b/src/southbridge/intel/lynxpoint/serialio.c
@@ -209,8 +209,8 @@
    	}
/* Save BAR0 and BAR1 to ACPI NVS */
-		gnvs->s0b[sio_index] = (u32)bar0->base;
-		gnvs->s1b[sio_index] = (u32)bar1->base;
+		gnvs_set_sio_bar0(gnvs, sio_index, (u32)bar0->base);
+		gnvs_set_sio_bar1(gnvs, sio_index, (u32)bar1->base);
    }
 }
diff --git a/src/southbridge/intel/wildcatpoint/nvs.h b/src/southbridge/intel/wildcatpoint/nvs.h
index b5fca62..712649d 100644
--- a/src/southbridge/intel/wildcatpoint/nvs.h
+++ b/src/southbridge/intel/wildcatpoint/nvs.h
@@ -53,4 +53,14 @@
 /* Used in SMM to find the ACPI GNVS address */
 global_nvs_t *smm_get_gnvs(void);
+static inline void gnvs_set_sio_bar0(global_nvs_t *gnvs, int sio_index, u32 bar0_base)
+{
+	gnvs->dev.bar0[sio_index] = bar0_base;
+}
+
+static inline void gnvs_set_sio_bar1(global_nvs_t *gnvs, int sio_index, u32 bar1_base)
+{
+	gnvs->dev.bar1[sio_index] = bar1_base;
+}
+
 #endif
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I62e80c009f8360b1d780db84eeddc6dc1799ee98
Gerrit-Change-Number: 42520
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons th3fanbus@gmail.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-MessageType: newchange



    