Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34772 )
Change subject: soc/mediatek: dsi: Refactor video timing calculation ......................................................................
soc/mediatek: dsi: Refactor video timing calculation
The video timing should be based on PHY timing. Some values can be ignored on 8173 because of fixed values in PHY but should be calculated for newer platforms like 8183.
BUG=b:80501386,b:117254947 TEST=make -j # board = oak and boots
Change-Id: Id3ad2edc08787414a74188f5050460e98222caf4 Signed-off-by: Hung-Te Lin hungte@chromium.org --- M src/soc/mediatek/common/dsi.c M src/soc/mediatek/mt8173/include/soc/dsi.h 2 files changed, 28 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/34772/1
diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 84ddaa1..17b127a 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -141,8 +141,9 @@ write32(&dsi0->dsi_txrx_ctrl, tmp_reg); }
-static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, - const struct edid *edid) +static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes, + const struct edid *edid, + const struct mtk_phy_timing *phy_timing) { u32 hsync_active_byte; u32 hbp_byte; @@ -152,6 +153,7 @@ u32 bytes_per_pixel; u32 packet_fmt; u32 hactive; + u32 data_phy_cycles;
bytes_per_pixel = mtk_dsi_get_bits_per_pixel(format) / 8; vbp_byte = edid->mode.vbl - edid->mode.vso - edid->mode.vspw - @@ -163,15 +165,27 @@ write32(&dsi0->dsi_vfp_nl, vfp_byte); write32(&dsi0->dsi_vact_nl, edid->mode.va);
+ unsigned int hspw = 0; if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) - hbp_byte = (edid->mode.hbl - edid->mode.hso - edid->mode.hspw - - edid->mode.hborder) * bytes_per_pixel - 10; - else - hbp_byte = (edid->mode.hbl - edid->mode.hso - - edid->mode.hborder) * bytes_per_pixel - 10; + hspw = edid->mode.hspw;
+ hbp_byte = (edid->mode.hbl - edid->mode.hso - hspw - edid->mode.hborder) + * bytes_per_pixel - 10; hsync_active_byte = edid->mode.hspw * bytes_per_pixel - 10; - hfp_byte = (edid->mode.hso - edid->mode.hborder) * bytes_per_pixel - 12; + hfp_byte = (edid->mode.hso - edid->mode.hborder) * bytes_per_pixel; + + data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare + + phy_timing->da_hs_zero + phy_timing->da_hs_exit + 2; + + u32 delta = 12; + if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) + delta += 6; + + u32 d_phy = data_phy_cycles * lanes + delta; + if (hfp_byte > d_phy) + hfp_byte -= d_phy; + else + printk(BIOS_ERR, "HFP less than d-phy, FPS < 60Hz\n");
write32(&dsi0->dsi_hsa_wc, hsync_active_byte); write32(&dsi0->dsi_hbp_wc, hbp_byte); @@ -198,7 +212,8 @@ hactive = edid->mode.ha; packet_fmt |= (hactive * bytes_per_pixel) & DSI_PS_WC;
- write32(&dsi0->dsi_psctrl, packet_fmt); + write32(&dsi0->dsi_psctrl, + PIXEL_STREAM_CUSTOM_HEADER << 26 | packet_fmt); }
static void mtk_dsi_start(void) @@ -223,7 +238,7 @@ mtk_dsi_phy_timing(data_rate, &phy_timing); mtk_dsi_rxtx_control(mode_flags, lanes); mtk_dsi_clk_hs_mode_disable(); - mtk_dsi_config_vdo_timing(mode_flags, format, edid); + mtk_dsi_config_vdo_timing(mode_flags, format, lanes, edid, &phy_timing); mtk_dsi_set_mode(mode_flags); mtk_dsi_clk_hs_mode_enable();
diff --git a/src/soc/mediatek/mt8173/include/soc/dsi.h b/src/soc/mediatek/mt8173/include/soc/dsi.h index 4d87406..e57bfc5 100644 --- a/src/soc/mediatek/mt8173/include/soc/dsi.h +++ b/src/soc/mediatek/mt8173/include/soc/dsi.h @@ -130,7 +130,9 @@ PACKED_PS_16BIT_RGB565 = (0 << 16), LOOSELY_PS_18BIT_RGB666 = (1 << 16), PACKED_PS_18BIT_RGB666 = (2 << 16), - PACKED_PS_24BIT_RGB888 = (3 << 16) + PACKED_PS_24BIT_RGB888 = (3 << 16), + + PIXEL_STREAM_CUSTOM_HEADER = 0, };
/* DSI_CMDQ_SIZE */
Hello Yu-Ping Wu, yongqiang niu, Julius Werner, You-Cheng Syu, jitao shi, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34772
to look at the new patch set (#3).
Change subject: soc/mediatek: dsi: Refactor video timing calculation ......................................................................
soc/mediatek: dsi: Refactor video timing calculation
The video timing should be based on PHY timing. Some values can be ignored on 8173 because of fixed values in PHY but should be calculated for newer platforms like 8183.
BUG=b:80501386,b:117254947 TEST=make -j # board = oak and boots
Change-Id: Id3ad2edc08787414a74188f5050460e98222caf4 Signed-off-by: Hung-Te Lin hungte@chromium.org --- M src/soc/mediatek/common/dsi.c M src/soc/mediatek/mt8173/include/soc/dsi.h 2 files changed, 28 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/34772/3
Hello Yu-Ping Wu, yongqiang niu, Julius Werner, You-Cheng Syu, jitao shi, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34772
to look at the new patch set (#4).
Change subject: soc/mediatek: dsi: Refactor video timing calculation ......................................................................
soc/mediatek: dsi: Refactor video timing calculation
The video timing should be based on PHY timing. Some values can be ignored on 8173 because of fixed values in PHY but should be calculated for newer platforms like 8183.
BUG=b:80501386,b:117254947 TEST=make -j # board = oak and boots
Change-Id: Id3ad2edc08787414a74188f5050460e98222caf4 Signed-off-by: Hung-Te Lin hungte@chromium.org --- M src/soc/mediatek/common/dsi.c M src/soc/mediatek/mt8173/include/soc/dsi.h 2 files changed, 26 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/34772/4
Hello Yu-Ping Wu, yongqiang niu, Julius Werner, You-Cheng Syu, jitao shi, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34772
to look at the new patch set (#5).
Change subject: soc/mediatek: dsi: Refactor video timing calculation ......................................................................
soc/mediatek: dsi: Refactor video timing calculation
The video timing should be based on PHY timing. Some values can be ignored on 8173 because of fixed values in PHY but should be calculated for newer platforms like 8183.
BUG=b:80501386,b:117254947 TEST=make -j # board = oak and boots
Change-Id: Id3ad2edc08787414a74188f5050460e98222caf4 Signed-off-by: Hung-Te Lin hungte@chromium.org --- M src/soc/mediatek/common/dsi.c M src/soc/mediatek/mt8173/include/soc/dsi.h 2 files changed, 26 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/34772/5
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34772 )
Change subject: soc/mediatek: dsi: Refactor video timing calculation ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34772/6/src/soc/mediatek/common/dsi... File src/soc/mediatek/common/dsi.c:
https://review.coreboot.org/c/coreboot/+/34772/6/src/soc/mediatek/common/dsi... PS6, Line 212: less than Is "not greater than" better?
https://review.coreboot.org/c/coreboot/+/34772/6/src/soc/mediatek/common/dsi... PS6, Line 240: PIXEL_STREAM_CUSTOM_HEADER << 26 What's the meaning of "0 << 26" here?
Hello Yu-Ping Wu, yongqiang niu, Julius Werner, You-Cheng Syu, jitao shi, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34772
to look at the new patch set (#7).
Change subject: soc/mediatek: dsi: Refactor video timing calculation ......................................................................
soc/mediatek: dsi: Refactor video timing calculation
The video timing should be based on PHY timing. Some values can be ignored on 8173 because of fixed values in PHY but should be calculated for newer platforms like 8183.
BUG=b:80501386,b:117254947 TEST=make -j # board = oak and boots
Change-Id: Id3ad2edc08787414a74188f5050460e98222caf4 Signed-off-by: Hung-Te Lin hungte@chromium.org --- M src/soc/mediatek/common/dsi.c M src/soc/mediatek/common/include/soc/dsi_common.h M src/soc/mediatek/mt8173/include/soc/dsi.h 3 files changed, 30 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/34772/7
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34772 )
Change subject: soc/mediatek: dsi: Refactor video timing calculation ......................................................................
Patch Set 8: Code-Review+1
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34772 )
Change subject: soc/mediatek: dsi: Refactor video timing calculation ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34772/10/src/soc/mediatek/common/ds... File src/soc/mediatek/common/dsi.c:
https://review.coreboot.org/c/coreboot/+/34772/10/src/soc/mediatek/common/ds... PS10, Line 212: printk(BIOS_ERR, "HFP is not greater than d-phy, FPS < 60Hz\n"); Please mention the consequences for the user.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34772 )
Change subject: soc/mediatek: dsi: Refactor video timing calculation ......................................................................
Patch Set 11: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/34772/11/src/soc/mediatek/common/ds... File src/soc/mediatek/common/dsi.c:
https://review.coreboot.org/c/coreboot/+/34772/11/src/soc/mediatek/common/ds... PS11, Line 209: u32 d_phy = data_phy_cycles * lanes + delta; nit: I hope you checked that this comes out to 12 for 8173, because I'm too lazy ^^
https://review.coreboot.org/c/coreboot/+/34772/11/src/soc/mediatek/common/ds... PS11, Line 268: mtk_dsi_config_vdo_timing(mode_flags, format, lanes, edid, &phy_timing); Oh, this is why you passed it out. Okay, fair enough.
Hello Yu-Ping Wu, Nicolas Boichat, Julius Werner, yongqiang niu, You-Cheng Syu, jitao shi, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34772
to look at the new patch set (#12).
Change subject: soc/mediatek: dsi: Refactor video timing calculation ......................................................................
soc/mediatek: dsi: Refactor video timing calculation
The video timing should be based on PHY timing. Some values can be ignored on 8173 because of fixed values in PHY but should be calculated for newer platforms like 8183.
BUG=b:80501386,b:117254947 TEST=make -j # board = oak and boots
Change-Id: Id3ad2edc08787414a74188f5050460e98222caf4 Signed-off-by: Hung-Te Lin hungte@chromium.org --- M src/soc/mediatek/common/dsi.c M src/soc/mediatek/common/include/soc/dsi_common.h M src/soc/mediatek/mt8173/dsi.c M src/soc/mediatek/mt8173/include/soc/dsi.h 4 files changed, 44 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/34772/12
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34772 )
Change subject: soc/mediatek: dsi: Refactor video timing calculation ......................................................................
Patch Set 12:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34772/11/src/soc/mediatek/common/ds... File src/soc/mediatek/common/dsi.c:
https://review.coreboot.org/c/coreboot/+/34772/11/src/soc/mediatek/common/ds... PS11, Line 209: u32 d_phy = data_phy_cycles * lanes + delta;
nit: I hope you checked that this comes out to 12 for 8173, because I'm too lazy ^^
Done
https://review.coreboot.org/c/coreboot/+/34772/11/src/soc/mediatek/common/ds... PS11, Line 268: mtk_dsi_config_vdo_timing(mode_flags, format, lanes, edid, &phy_timing);
Oh, this is why you passed it out. Okay, fair enough.
Ack
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34772 )
Change subject: soc/mediatek: dsi: Refactor video timing calculation ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34772/10/src/soc/mediatek/common/ds... File src/soc/mediatek/common/dsi.c:
https://review.coreboot.org/c/coreboot/+/34772/10/src/soc/mediatek/common/ds... PS10, Line 212: printk(BIOS_ERR, "HFP is not greater than d-phy, FPS < 60Hz\n");
Please mention the consequences for the user.
Done
Hello Yu-Ping Wu, Nicolas Boichat, Julius Werner, yongqiang niu, You-Cheng Syu, jitao shi, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34772
to look at the new patch set (#13).
Change subject: soc/mediatek: dsi: Refactor video timing calculation ......................................................................
soc/mediatek: dsi: Refactor video timing calculation
The video timing should be based on PHY timing. Some values can be ignored on 8173 because of fixed values in PHY but should be calculated for newer platforms like 8183.
BUG=b:80501386,b:117254947 TEST=make -j # board = oak and boots
Change-Id: Id3ad2edc08787414a74188f5050460e98222caf4 Signed-off-by: Hung-Te Lin hungte@chromium.org --- M src/soc/mediatek/common/dsi.c M src/soc/mediatek/common/include/soc/dsi_common.h M src/soc/mediatek/mt8173/dsi.c M src/soc/mediatek/mt8173/include/soc/dsi.h 4 files changed, 45 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/34772/13
Hello Yu-Ping Wu, Nicolas Boichat, Julius Werner, yongqiang niu, You-Cheng Syu, jitao shi, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34772
to look at the new patch set (#14).
Change subject: soc/mediatek: dsi: Refactor video timing calculation ......................................................................
soc/mediatek: dsi: Refactor video timing calculation
The video timing should be based on PHY timing. Some values can be ignored on 8173 because of fixed values in PHY but should be calculated for newer platforms like 8183.
BUG=b:80501386,b:117254947 TEST=make -j # board = oak and boots
Change-Id: Id3ad2edc08787414a74188f5050460e98222caf4 Signed-off-by: Hung-Te Lin hungte@chromium.org --- M src/soc/mediatek/common/dsi.c M src/soc/mediatek/common/include/soc/dsi_common.h M src/soc/mediatek/mt8173/dsi.c M src/soc/mediatek/mt8173/include/soc/dsi.h 4 files changed, 37 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/34772/14
Hello Yu-Ping Wu, Nicolas Boichat, Julius Werner, yongqiang niu, You-Cheng Syu, jitao shi, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34772
to look at the new patch set (#15).
Change subject: soc/mediatek: dsi: Refactor video timing calculation ......................................................................
soc/mediatek: dsi: Refactor video timing calculation
The video timing should be based on PHY timing. Some values can be ignored on 8173 because of fixed values in PHY but should be calculated for newer platforms like 8183.
BUG=b:80501386,b:117254947 TEST=make -j # board = oak and boots
Change-Id: Id3ad2edc08787414a74188f5050460e98222caf4 Signed-off-by: Hung-Te Lin hungte@chromium.org --- M src/soc/mediatek/common/dsi.c M src/soc/mediatek/common/include/soc/dsi_common.h M src/soc/mediatek/mt8173/dsi.c M src/soc/mediatek/mt8173/include/soc/dsi.h 4 files changed, 37 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/34772/15
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34772 )
Change subject: soc/mediatek: dsi: Refactor video timing calculation ......................................................................
Patch Set 15: Code-Review+2
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34772 )
Change subject: soc/mediatek: dsi: Refactor video timing calculation ......................................................................
Patch Set 15:
Needs a rebase for merge.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34772 )
Change subject: soc/mediatek: dsi: Refactor video timing calculation ......................................................................
Patch Set 16:
Rebased
Julius Werner has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34772 )
Change subject: soc/mediatek: dsi: Refactor video timing calculation ......................................................................
soc/mediatek: dsi: Refactor video timing calculation
The video timing should be based on PHY timing. Some values can be ignored on 8173 because of fixed values in PHY but should be calculated for newer platforms like 8183.
BUG=b:80501386,b:117254947 TEST=make -j # board = oak and boots
Change-Id: Id3ad2edc08787414a74188f5050460e98222caf4 Signed-off-by: Hung-Te Lin hungte@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/34772 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Julius Werner jwerner@chromium.org --- M src/soc/mediatek/common/dsi.c M src/soc/mediatek/common/include/soc/dsi_common.h M src/soc/mediatek/mt8173/dsi.c M src/soc/mediatek/mt8173/include/soc/dsi.h 4 files changed, 37 insertions(+), 11 deletions(-)
Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved
diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 1a768a5..392b02d 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -170,8 +170,9 @@ write32(&dsi0->dsi_txrx_ctrl, tmp_reg); }
-static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, - const struct edid *edid) +static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes, + const struct edid *edid, + const struct mtk_phy_timing *phy_timing) { u32 hsync_active_byte; u32 hbp_byte; @@ -181,6 +182,7 @@ u32 bytes_per_pixel; u32 packet_fmt; u32 hactive; + u32 data_phy_cycles;
bytes_per_pixel = DIV_ROUND_UP(mtk_dsi_get_bits_per_pixel(format), 8); vbp_byte = edid->mode.vbl - edid->mode.vso - edid->mode.vspw - @@ -192,15 +194,30 @@ write32(&dsi0->dsi_vfp_nl, vfp_byte); write32(&dsi0->dsi_vact_nl, edid->mode.va);
+ unsigned int hspw = 0; if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) - hbp_byte = (edid->mode.hbl - edid->mode.hso - edid->mode.hspw - - edid->mode.hborder) * bytes_per_pixel - 10; - else - hbp_byte = (edid->mode.hbl - edid->mode.hso - - edid->mode.hborder) * bytes_per_pixel - 10; + hspw = edid->mode.hspw;
+ hbp_byte = (edid->mode.hbl - edid->mode.hso - hspw - edid->mode.hborder) + * bytes_per_pixel - 10; hsync_active_byte = edid->mode.hspw * bytes_per_pixel - 10; - hfp_byte = (edid->mode.hso - edid->mode.hborder) * bytes_per_pixel - 12; + hfp_byte = (edid->mode.hso - edid->mode.hborder) * bytes_per_pixel; + + data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare + + phy_timing->da_hs_zero + phy_timing->da_hs_exit + 2; + + u32 delta = 12; + if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) + delta += 6; + + u32 d_phy = phy_timing->d_phy; + if (d_phy == 0) + d_phy = data_phy_cycles * lanes + delta; + if (hfp_byte > d_phy) + hfp_byte -= d_phy; + else + printk(BIOS_ERR, "HFP is not greater than d-phy, FPS < 60Hz " + "and the panel may not work properly.\n");
write32(&dsi0->dsi_hsa_wc, hsync_active_byte); write32(&dsi0->dsi_hbp_wc, hbp_byte); @@ -227,7 +244,9 @@ hactive = edid->mode.ha; packet_fmt |= (hactive * bytes_per_pixel) & DSI_PS_WC;
- write32(&dsi0->dsi_psctrl, packet_fmt); + write32(&dsi0->dsi_psctrl, + PIXEL_STREAM_CUSTOM_HEADER << DSI_PSCON_CUSTOM_HEADER_SHIFT | + packet_fmt); }
static void mtk_dsi_start(void) @@ -252,7 +271,7 @@ mtk_dsi_phy_timing(data_rate, &phy_timing); mtk_dsi_rxtx_control(mode_flags, lanes); mtk_dsi_clk_hs_mode_disable(); - mtk_dsi_config_vdo_timing(mode_flags, format, edid); + mtk_dsi_config_vdo_timing(mode_flags, format, lanes, edid, &phy_timing); mtk_dsi_set_mode(mode_flags); mtk_dsi_clk_hs_mode_enable();
diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h index bfdd407..0738876 100644 --- a/src/soc/mediatek/common/include/soc/dsi_common.h +++ b/src/soc/mediatek/common/include/soc/dsi_common.h @@ -129,7 +129,9 @@ PACKED_PS_16BIT_RGB565 = (0 << 16), LOOSELY_PS_18BIT_RGB666 = (1 << 16), PACKED_PS_18BIT_RGB666 = (2 << 16), - PACKED_PS_24BIT_RGB888 = (3 << 16) + PACKED_PS_24BIT_RGB888 = (3 << 16), + + DSI_PSCON_CUSTOM_HEADER_SHIFT = 26, };
/* DSI_CMDQ_SIZE */ @@ -318,6 +320,8 @@ u8 clk_hs_prepare; u8 clk_hs_post; u8 clk_hs_exit; + + u32 d_phy; };
/* Functions that each SOC should provide. */ diff --git a/src/soc/mediatek/mt8173/dsi.c b/src/soc/mediatek/mt8173/dsi.c index 32f4f1c..b6ff0bc 100644 --- a/src/soc/mediatek/mt8173/dsi.c +++ b/src/soc/mediatek/mt8173/dsi.c @@ -122,6 +122,8 @@
timing->da_hs_sync = 0; timing->clk_hs_exit = 2 * lpx; + + timing->d_phy = 12; }
void mtk_dsi_pin_drv_ctrl(void) diff --git a/src/soc/mediatek/mt8173/include/soc/dsi.h b/src/soc/mediatek/mt8173/include/soc/dsi.h index 99c51e6..43cbdcb 100644 --- a/src/soc/mediatek/mt8173/include/soc/dsi.h +++ b/src/soc/mediatek/mt8173/include/soc/dsi.h @@ -22,6 +22,7 @@ #define MTK_DSI_MIPI_RATIO_NUMERATOR 102 #define MTK_DSI_MIPI_RATIO_DENOMINATOR 100 #define MTK_DSI_DATA_RATE_MIN_MHZ 50 +#define PIXEL_STREAM_CUSTOM_HEADER 0
/* MIPITX is SOC specific and cannot live in common. */
-
Hung-Te Lin (Code Review) -
Julius Werner (Code Review)
-
Paul Menzel (Code Review)
-
Yu-Ping Wu (Code Review)