Change in coreboot[master]: soc/intel/alderlake: Drop unused `PrmrrSize` from devicetree

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52108 )

Change subject: soc/intel/alderlake: Drop unused `PrmrrSize` from devicetree
......................................................................

soc/intel/alderlake: Drop unused `PrmrrSize` from devicetree

The `PrmrrSize` FSP-M UPD is set using `get_valid_prmrr_size()`. As the
devicetree option's value is not used anywhere, drop it.

Change-Id: Ib6fb77b03a4648adbd8b23c160cfba94d142a2d2
Signed-off-by: Angel Pons 
---
M src/mainboard/intel/adlrvp/devicetree.cb
M src/mainboard/intel/adlrvp/devicetree_m.cb
M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
M src/soc/intel/alderlake/chip.h
4 files changed, 0 insertions(+), 15 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/52108/1

diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index cade987..9ad0a4f 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -50,8 +50,6 @@
    register "gpio_pm[COMM_4]" = "0"
    register "gpio_pm[COMM_5]" = "0"

-	register "PrmrrSize" = "0"
-
    # Enable PCH PCIE RP 5 using CLK 2
    register "pch_pcie_rp[PCH_RP(5)]" = "{
    	.clk_src = 2,
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb
index 3094010..3e40691 100644
--- a/src/mainboard/intel/adlrvp/devicetree_m.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_m.cb
@@ -36,8 +36,6 @@
    register "gen3_dec" = "0x00fc0901"
    register "gen4_dec" = "0x000c0081"

-	register "PrmrrSize" = "0"
-
    #Enable PCH PCIE RP 4 using CLK 5
    register "pch_pcie_rp[PCH_RP(4)]" = "{
    	.clk_src = 5,
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
index 98f6400..dfeb32b 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
@@ -43,7 +43,6 @@
    register "gen2_dec" = "0x000c0201"
    # EC memory map range is 0x900-0x9ff
    register "gen3_dec" = "0x00fc0901"
-	register "PrmrrSize" = "0"

# Enable PCH PCIE RP 5 using CLK 1
    register "pch_pcie_rp[PCH_RP(5)]" = "{
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 92d53a9..524a61a 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -161,16 +161,6 @@

/* Enable C6 DRAM */
    uint8_t enable_c6dram;
-	/*
-	 * PRMRR size setting with below options
-	 * Disable: 0x0
-	 * 32MB: 0x2000000
-	 * 64MB: 0x4000000
-	 * 128 MB: 0x8000000
-	 * 256 MB: 0x10000000
-	 * 512 MB: 0x20000000
-	 */
-	uint32_t PrmrrSize;
    uint8_t PmTimerDisabled;
    /*
     * SerialIO device mode selection: