Change in coreboot[master]: soc/intel/cannonlake: Use common bootblock basecode

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Furquan Shaikh, Angel Pons, Subrata Banik, Michael Niewöhner, Patrick Rudolph.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50956 )

Change subject: soc/intel/cannonlake: Use common bootblock basecode
......................................................................

Patch Set 2:

(1 comment)

File src/soc/intel/cannonlake/bootblock/bootblock.c:

https://review.coreboot.org/c/coreboot/+/50956/comment/29e3da3f_8017028b 
PS2, Line 64: 	/*
            : 	 * Clear the GPI interrupt status and enable registers. These
            : 	 * registers do not get reset to default state when booting from S5.
            : 	 */
            : 	gpi_clear_int_cfg();
> Oh, thanks for spotting this oversight. […]

How about bootblock_pch_init() for now, and I'll try to follow up later to move it to common code .