New patch to review for coreboot: d93bd26 intel/fsp_baytrail: Fix logging of ISPEnable option

[David Imhoff]

David Imhoff ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10126

-gerrit

commit d93bd263b66d83fff4e22826e465aae8fac326df
Author: David Imhoff 
Date:   Wed May 6 21:42:37 2015 +0200

intel/fsp_baytrail: Fix logging of ISPEnable option

Before this fix the value of PcdEnableSdio was printed as the MIPI/ISP
    configuration option.

TEST=Built and booted on Minnowboard Max

Change-Id: Ia9b02d520f4e615f90b45935456b9d97c5d00f11
    Signed-off-by: David Imhoff 
---
 src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
index eb068ba..5bfcfd5 100644
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
@@ -168,14 +168,14 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U
    			if (FspInfo->ImageRevision >= FSP_GOLD3_REV_ID) {
    				UpdData->ISPEnable = dev->enabled;
    			} else {
-					/* Gold2 and earlier FSP: ISPEnable is the filed	*/
+					/* Gold2 and earlier FSP: ISPEnable is the field	*/
    				/* next to PcdGttSize in UPD_DATA_REGION struct		*/
    				*(&(UpdData->PcdGttSize)+sizeof(UINT8)) = dev->enabled;
    				printk (FSP_INFO_LEVEL,
    					"Baytrail Gold2 or earlier FSP, adjust ISPEnable offset.\n");
    			}
    			printk(FSP_INFO_LEVEL, "MIPI/ISP:\t\t%s\n",
-						UpdData->PcdEnableSdio?"Enabled":"Disabled");
+						dev->enabled?"Enabled":"Disabled");
    			break;
    		case EMMC_DEV_FUNC: /* EMMC 4.1*/
    			if ((dev->enabled) &&