HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37758 )
Change subject: cpu/intel: Remove ROMCC header guards and code ......................................................................
cpu/intel: Remove ROMCC header guards and code
Intel's platforms use a GCC compiled bootblock.
Change-Id: I779d7115fee75df9356873e9cc66d43280821812 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/romstage.c M src/cpu/intel/microcode/Kconfig M src/cpu/intel/microcode/microcode.c 4 files changed, 2 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/37758/1
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 5a668c4..330d8ee 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -29,10 +29,8 @@
bootblock_pre_c_entry:
-#if !CONFIG(ROMCC_BOOTBLOCK) movl $cache_as_ram, %esp /* return address */ jmp check_mtrr /* Check if CPU properly reset */ -#endif
cache_as_ram: post_code(0x20) diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 1f8eb9a..bd6a5a9 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -71,19 +71,6 @@ /* We do not return here. */ }
-#if CONFIG(ROMCC_BOOTBLOCK) -/* This wrapper enables easy transition away from ROMCC_BOOTBLOCK - * keeping changes in cache_as_ram.S easy to manage. - */ -asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) -{ - timestamp_init(base_timestamp); - timestamp_add_now(TS_START_ROMSTAGE); - romstage_main(bist); -} -#endif - - /* We don't carry BIST from bootblock in a good location to read from. * Any error should have been reported in bootblock already. */ diff --git a/src/cpu/intel/microcode/Kconfig b/src/cpu/intel/microcode/Kconfig index 73afe0b..238aad7 100644 --- a/src/cpu/intel/microcode/Kconfig +++ b/src/cpu/intel/microcode/Kconfig @@ -1,7 +1,7 @@ config MICROCODE_UPDATE_PRE_RAM bool depends on SUPPORT_CPU_UCODE_IN_CBFS - default y if !ROMCC_BOOTBLOCK + default y help Select this option if you want to update the microcode during the cache as ram setup. diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 80470bf..90138be 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -15,11 +15,7 @@
#include <stdint.h> #include <stddef.h> -#if !defined(__ROMCC__) #include <cbfs.h> -#else -#include <arch/cbfs.h> -#endif #include <arch/cpu.h> #include <console/console.h> #include <cpu/x86/msr.h> @@ -141,22 +137,11 @@ unsigned int x86_model, x86_family; msr_t msr;
-#ifdef __ROMCC__ - struct cbfs_file *microcode_file; - - microcode_file = walkcbfs_head((char *) MICROCODE_CBFS_FILE); - if (!microcode_file) - return NULL; - - ucode_updates = CBFS_SUBHEADER(microcode_file); - microcode_len = ntohl(microcode_file->len); -#else ucode_updates = cbfs_boot_map_with_leak(MICROCODE_CBFS_FILE, CBFS_TYPE_MICROCODE, µcode_len); if (ucode_updates == NULL) return NULL; -#endif
/* CPUID sets MSR 0x8B if a microcode update has been loaded. */ msr.lo = 0; @@ -201,8 +186,7 @@ microcode_len -= update_size; }
- /* ROMCC doesn't like NULL. */ - return (void *)0; + return NULL; }
void intel_update_microcode_from_cbfs(void)
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37758
to look at the new patch set (#2).
Change subject: cpu/intel: Remove ROMCC header guards and code ......................................................................
cpu/intel: Remove ROMCC header guards and code
Intel's platforms use a GCC compiled bootblock.
Change-Id: I779d7115fee75df9356873e9cc66d43280821812 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/romstage.c M src/cpu/intel/microcode/Kconfig M src/cpu/intel/microcode/microcode.c 4 files changed, 2 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/37758/2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37758 )
Change subject: cpu/intel: Remove ROMCC header guards and code ......................................................................
Patch Set 2: Code-Review+2
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37758 )
Change subject: cpu/intel: Remove ROMCC header guards and code ......................................................................
Patch Set 2: Code-Review+1
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37758 )
Change subject: cpu/intel: Remove ROMCC header guards and code ......................................................................
cpu/intel: Remove ROMCC header guards and code
Intel's platforms use a GCC compiled bootblock.
Change-Id: I779d7115fee75df9356873e9cc66d43280821812 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/37758 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-by: Nico Huber nico.h@gmx.de --- M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/romstage.c M src/cpu/intel/microcode/Kconfig M src/cpu/intel/microcode/microcode.c 4 files changed, 2 insertions(+), 34 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Nico Huber: Looks good to me, but someone else must approve
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 5a668c4..4dee0a8 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -28,11 +28,8 @@ _cache_as_ram_setup:
bootblock_pre_c_entry: - -#if !CONFIG(ROMCC_BOOTBLOCK) movl $cache_as_ram, %esp /* return address */ jmp check_mtrr /* Check if CPU properly reset */ -#endif
cache_as_ram: post_code(0x20) diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 1f8eb9a..bd6a5a9 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -71,19 +71,6 @@ /* We do not return here. */ }
-#if CONFIG(ROMCC_BOOTBLOCK) -/* This wrapper enables easy transition away from ROMCC_BOOTBLOCK - * keeping changes in cache_as_ram.S easy to manage. - */ -asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) -{ - timestamp_init(base_timestamp); - timestamp_add_now(TS_START_ROMSTAGE); - romstage_main(bist); -} -#endif - - /* We don't carry BIST from bootblock in a good location to read from. * Any error should have been reported in bootblock already. */ diff --git a/src/cpu/intel/microcode/Kconfig b/src/cpu/intel/microcode/Kconfig index 73afe0b..238aad7 100644 --- a/src/cpu/intel/microcode/Kconfig +++ b/src/cpu/intel/microcode/Kconfig @@ -1,7 +1,7 @@ config MICROCODE_UPDATE_PRE_RAM bool depends on SUPPORT_CPU_UCODE_IN_CBFS - default y if !ROMCC_BOOTBLOCK + default y help Select this option if you want to update the microcode during the cache as ram setup. diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 80470bf..90138be 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -15,11 +15,7 @@
#include <stdint.h> #include <stddef.h> -#if !defined(__ROMCC__) #include <cbfs.h> -#else -#include <arch/cbfs.h> -#endif #include <arch/cpu.h> #include <console/console.h> #include <cpu/x86/msr.h> @@ -141,22 +137,11 @@ unsigned int x86_model, x86_family; msr_t msr;
-#ifdef __ROMCC__ - struct cbfs_file *microcode_file; - - microcode_file = walkcbfs_head((char *) MICROCODE_CBFS_FILE); - if (!microcode_file) - return NULL; - - ucode_updates = CBFS_SUBHEADER(microcode_file); - microcode_len = ntohl(microcode_file->len); -#else ucode_updates = cbfs_boot_map_with_leak(MICROCODE_CBFS_FILE, CBFS_TYPE_MICROCODE, µcode_len); if (ucode_updates == NULL) return NULL; -#endif
/* CPUID sets MSR 0x8B if a microcode update has been loaded. */ msr.lo = 0; @@ -201,8 +186,7 @@ microcode_len -= update_size; }
- /* ROMCC doesn't like NULL. */ - return (void *)0; + return NULL; }
void intel_update_microcode_from_cbfs(void)
-
HAOUAS Elyes (Code Review) -
Kyösti Mälkki (Code Review)
-
Nico Huber (Code Review)