Change in coreboot[master]: soc/mediatek/mt8186: Adjust usage of SRAM L2C

[Rex-BC Chen (Code Review)]

Attention is currently required from: Hung-Te Lin, Rex-BC Chen.
Hello Hung-Te Lin, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/60316

to look at the new patch set (#5).

Change subject: soc/mediatek/mt8186: Adjust usage of SRAM L2C
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soc/mediatek/mt8186: Adjust usage of SRAM L2C

We use parts of SRAM_L2C as the memory of PRERAM_CBMEM_CONSOLE before
DRAM calibration. When we check cbmem, we found the content of this
memory is unreadable.

The L3 (can be used as SRAM_L2C) is 1MB in total. However the BootROM
has configured only half of L2/L3 cache as SRAM. Therefore, decrease
the size of each SRAM region to fit into the first half of the cache.

BUG=b:207725851
TEST=Bootblock log looked good in `cbmem -c`

Signed-off-by: Rex-BC Chen 
Change-Id: I6041767a1ac0a48ecdda29a0c35d90acf6ad0ef2
---
M src/soc/mediatek/mt8186/include/soc/memlayout.ld
1 file changed, 11 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/60316/5