[XS] Change in coreboot[main]: mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2

[Ren Kuo (Code Review)]

Attention is currently required from: David Wu, Karthik Ramasubramanian, Subrata Banik.

Hello David Wu, Karthik Ramasubramanian, Subrata Banik,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/85533?usp=email

to look at the new patch set (#3).

Change subject: mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2
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mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2

The decision to set PCIe root port 5 speed to Gen2 is based on experiment setup for b/376156567 and analysis results in comment #86.
The setting will fix the issue of Wifi 7 M.2 module doesn't work.

BUG=b:376156567
TEST=Boot to OS and then check link speed.
     Use command: lspci -vv | grep 'LnkSta'

Before
     LnkSta: Speed 8GT/s (downgraded), Width x1
     After
     LnkSta: Speed 5GT/s (downgraded), Width x1

Change-Id: I9e8a02061251f73ee5ec2299e62fa423ff4b0965
Signed-off-by: Ren Kuo 
---
M src/mainboard/google/brox/variants/jubilant/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/85533/3