Change in coreboot[master]: soc/mediatek: Add PCIe support

[Nico Huber (Code Review)]

Attention is currently required from: Arthur Heymans, Shelley Chen, Hung-Te Lin, Furquan Shaikh, Angel Pons, Yu-Ping Wu, Jianjun Wang.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56791 )

Change subject: soc/mediatek: Add PCIe support
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Patch Set 9:

(1 comment)

File src/soc/mediatek/common/pcie.c:

https://review.coreboot.org/c/coreboot/+/56791/comment/c6b01df1_685104b1 
PS9, Line 103: devfn = (dev >> 12) & 0xf;
             : 	val = PCIE_CFG_HEADER((dev >> 20) & 0xf, devfn);
> This seems unnecessarily complex. Looks like this is equivalent: […]

It looks broken. `devfn` should be 8 bits wide unless there are
2 device at most in the whole PCI hierarchy. And given the mask
in PCIE_CFG_BUS() above, I guess the bus number should be 8 bits
wide too. To be readable, this should suit:

devfn = PCI_DEV2DEVFN(dev);
    bus   = PCI_DEV2SEGBUS(dev);
    val   = PCIE_CFG_HEADER(bus, devfn);

OTOH, if the 4-bit fields are correct, the macros should be fixed
to reflect that and a comment explaining the limits would be nice.