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I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/55252
to look at the new patch set (#5).
Change subject: soc/intel/{common,alderlake}: Use generic name "Alderlake Platform" ......................................................................
soc/intel/{common,alderlake}: Use generic name "Alderlake Platform"
The patch renames all ADL-P and ADL-M Silicon CPUID macros and define generic name "Alderlake Platform" as macro value.
The macros are renamed as below: CPUID_ALDERLAKE_P_A0 -> CPUID_ALDERLAKE_A0 CPUID_ALDERLAKE_P_B0 -> CPUID_ALDERLAKE_B0 CPUID_ALDERLAKE_M_A0 -> CPUID_ALDERLAKE_C0
TEST=Verify boot on Brya. After change, relevent coreboot logs appear as below:
CPU: ID 906a1, Alderlake Platform, ucode: 00000119 CPU: AES supported, TXT supported, VT supported MCH: device id 4601 (rev 03) is Alderlake-P PCH: device id 5181 (rev 00) is Alderlake-P SKU IGD: device id 46b0 (rev 04) is Alderlake P GT2
Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Change-Id: Ia06d2b62d4194edd4e104d49b340ac23305a4c15 --- M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/include/intelblocks/mp_init.h 3 files changed, 9 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/55252/5