Change in coreboot[master]: cezanne/psp_verstage: update SRAM address

[Kangheui Won (Code Review)]

Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53904 )

Change subject: cezanne/psp_verstage: update SRAM address
......................................................................

cezanne/psp_verstage: update SRAM address

Loading address and size for the user app has been changed with recent
PSP release.

Signed-off-by: Kangheui Won 
Change-Id: If247cdf3413c6a10f4b3c92fb7e43dd1057865d9
---
M src/soc/amd/cezanne/include/soc/psp_verstage_addr.h
1 file changed, 4 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/53904/1

diff --git a/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h b/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h
index bdc46cb..569d6e1 100644
--- a/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h
+++ b/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h
@@ -8,8 +8,8 @@
  * header for the user app (verstage) must be mapped.
  * Size is 0x14000 bytes
  */
-#define PSP_SRAM_START			0x36000
-#define PSP_SRAM_SIZE			(80K)
+#define PSP_SRAM_START			0x26000
+#define PSP_SRAM_SIZE			(148K)
 #define VERSTAGE_START			PSP_SRAM_START

/*
@@ -17,7 +17,7 @@
  * and make the size a multiple of 4k
  */

-#define PSP_VERSTAGE_STACK_START	0x49000
-#define PSP_VERSTAGE_STACK_SIZE		(4K)
+#define PSP_VERSTAGE_STACK_START	0x41000
+#define PSP_VERSTAGE_STACK_SIZE		(40K)

#endif  /* AMD_CEZANNE_PSP_VERSTAGE_ADDR_H */