Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/23775
Change subject: soc/cavium: Merge WDT and timer ......................................................................
soc/cavium: Merge WDT and timer
Merge WDT code into timer. Clean WDT and timer. Add support for multiple watchdogs. Move everything to common folder.
Tested the watchdog, works fine.
Change-Id: I12b7828a108fc6fd764dc8dfc716615033acb885 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/mainboard/cavium/cn8100_sff_evb/bootblock.c M src/mainboard/cavium/cn8100_sff_evb/romstage.c M src/soc/cavium/cn81xx/Makefile.inc M src/soc/cavium/cn81xx/bootblock.c D src/soc/cavium/cn81xx/include/soc/timer.h D src/soc/cavium/cn81xx/timer.c M src/soc/cavium/common/Makefile.inc A src/soc/cavium/common/include/soc/timer.h A src/soc/cavium/common/timer.c D src/soc/cavium/common/wdt.c 10 files changed, 247 insertions(+), 262 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/23775/1
diff --git a/src/mainboard/cavium/cn8100_sff_evb/bootblock.c b/src/mainboard/cavium/cn8100_sff_evb/bootblock.c index 6b5f45c..f1e3d60 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/bootblock.c +++ b/src/mainboard/cavium/cn8100_sff_evb/bootblock.c @@ -58,22 +58,7 @@ void bootblock_mainboard_init(void) { struct spi_slave slave; -#if 0 - if (rkclk_was_watchdog_reset()) - reboot_from_watchdog(); -#endif - - printk(BIOS_DEBUG, "hello from %s, %s addr: %p\n", __func__, __func__, &bootblock_mainboard_init); - -#if 0 - printk(BIOS_DEBUG, "spot checking timer...\n"); - int i; - for (i = 0; i < 5; i++) { - printk(BIOS_DEBUG, "i: %d\n", i); - mdelay(1000); - } -#endif - + printk(BIOS_DEBUG, "hello from %s, addr: %p\n", __func__, &bootblock_mainboard_init); printk(BIOS_DEBUG, "%s: spi_ctrlr_bus_map_count: %zu, &spi_ctrlr_bus_map_count: %p\n", __func__, spi_ctrlr_bus_map_count, &spi_ctrlr_bus_map_count); slave.ctrlr = spi_ctrlr_bus_map[0].ctrlr; diff --git a/src/mainboard/cavium/cn8100_sff_evb/romstage.c b/src/mainboard/cavium/cn8100_sff_evb/romstage.c index 096affe..55aa529 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/romstage.c +++ b/src/mainboard/cavium/cn8100_sff_evb/romstage.c @@ -82,7 +82,7 @@ // bdk_boot_bgx(); /* ethernet */ // bdk_boot_usb();
- watchdog_poke(); + watchdog_poke(0);
// bdk_boot_gpio(); // bdk_boot_pcie(); diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc index 6c129e8..91d71dd 100644 --- a/src/soc/cavium/cn81xx/Makefile.inc +++ b/src/soc/cavium/cn81xx/Makefile.inc @@ -31,8 +31,6 @@ bootblock-y += l2c.c bootblock-y += mmu_operations.c #bootblock-y += sdram.c -bootblock-y += timer.c -bootblock-y += ../common/wdt.c
romstage-y += twsi.c
@@ -77,8 +75,7 @@ #verstage-y += ../common/i2c.c #verstage-y += spi.c #verstage-$(CONFIG_DRIVERS_UART) += uart.c -#verstage-y += timer.c -verstage-y += ../common/wdt.c +
################################################################################
@@ -87,10 +84,8 @@ romstage-$(CONFIG_DRIVERS_UART) += uart.c romstage-y += mmu_operations.c #romstage-y += ../common/pwm.c -romstage-y += timer.c #romstage-y += gpio.c #romstage-y += ../common/gpio.c -romstage-y += ../common/wdt.c
################################################################################
@@ -103,8 +98,6 @@ #ramstage-y += gpio.c #ramstage-y += ../common/i2c.c #ramstage-y += soc.c -ramstage-y += timer.c -ramstage-y += ../common/wdt.c
ramstage-y += bl31_plat_params.c #BL31_MAKEARGS += PLAT=qemu M0_CROSS_COMPILE="$(CROSS_COMPILE_arm)" diff --git a/src/soc/cavium/cn81xx/bootblock.c b/src/soc/cavium/cn81xx/bootblock.c index 2be7b6b..66fb98c 100644 --- a/src/soc/cavium/cn81xx/bootblock.c +++ b/src/soc/cavium/cn81xx/bootblock.c @@ -101,7 +101,9 @@ /* initialize system registers */ init_sysreg();
- watchdog_poke(); + /* Set watchdog to 5 seconds timeout */ + watchdog_set(0, 5000); + watchdog_poke(0);
/* TODO: additional clock init? */ /* TODO: additional trustzone init? mark cache or RAM non-secure? */ diff --git a/src/soc/cavium/cn81xx/include/soc/timer.h b/src/soc/cavium/cn81xx/include/soc/timer.h deleted file mode 100644 index 788e998..0000000 --- a/src/soc/cavium/cn81xx/include/soc/timer.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright 2017-present Facebook, Inc. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __SOC_CAVIUM_CN81XX_TIMER_H__ -#define __SOC_CAVIUM_CN81XX_TIMER_H__ - -#include <inttypes.h> -#include <soc/addressmap.h> -#include <types.h> -#include <timer.h> - -/* Global System Timers Unit (GTI) registers */ -struct cn81xx_timer { - u32 cc_cntcr; - u32 cc_cntsr; - u64 cc_cntcv; - u8 rsvd[0x10]; - u32 cc_cntfid0; - u32 cc_cntfid1; - u8 rsvd2[0x98]; - u32 cc_cntrate; - u32 cc_cntracc; - u64 cc_cntadd; - u64 cc_cntmb; - u64 cc_cntmbts; - u64 cc_cntmb_int; - u64 cc_cntmb_int_set; - u64 cc_cntmb_int_ena_clr; - u64 cc_cntmb_int_ena_set; - u64 cc_imp_ctl; - u8 skip[0x1fef8]; - u32 ctl_cntfrq; - u32 ctl_cntnsar; - u32 ctl_cnttidr; - u8 rsvd3[0x34]; - u32 ctl_cntacr0; - u8 skip2[0x1ffb8]; - u64 cwd_wdog0; /* there are 48 of these */ - u8 skip3[0xfff8]; - u64 cwd_poke0; /* there are 48 of these */ -}; -check_member(cn81xx_timer, cc_imp_ctl, 0x100); -check_member(cn81xx_timer, ctl_cntacr0, 0x20040); -check_member(cn81xx_timer, cwd_wdog0, 0x40000); -check_member(cn81xx_timer, cwd_poke0, 0x50000); - -/* Watchdog functions */ -/* TODO: Currently we assume we're working with WDT0. We could pass - * in a cn81xx_timer as a parameter in case we want to use others. */ -void watchdog_set(unsigned int timeout_ms); -void watchdog_poke(void); -void watchdog_disable(void); -int watchdog_is_running(void); - -#define GTI_CC_CNTCR_EN (1 << 0) -#define GTI_CC_CNTCR_HDBG (1 << 1) -#define GTI_CC_CNTCR_FCREQ (1 << 8) - -#define GTI_CC_CNTSR_DBGH (1 << 1) -#define GTI_CC_CNTSR_FCACK (1 << 8) - -#define GTI_CWD_WDOG_MODE_SHIFT 0 -#define GTI_CWD_WDOG_MODE_MASK 0x3 -#define GTI_CWD_WDOG_STATE_SHIFT 2 -#define GTI_CWD_WDOG_STATE_MASK 0x3 -#define GTI_CWD_WDOG_LEN_SHIFT 4 -#define GTI_CWD_WDOG_LEN_MASK 0xffff -#define GTI_CWD_WDOG_CNT_SHIFT 20 -#define GTI_CWD_WDOG_CNT_MASK 0xffffff -#define GTI_CWD_WDOC_DSTOP (1 << 44) -#define GTI_CWD_WDOC_GSTOP (1 << 45) - -#endif /* __SOC_CAVIUM_CN81XX_TIMER_H__ */ diff --git a/src/soc/cavium/cn81xx/timer.c b/src/soc/cavium/cn81xx/timer.c deleted file mode 100644 index a60d5cb..0000000 --- a/src/soc/cavium/cn81xx/timer.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2003-2017 Cavium Inc. (support@cavium.com). All rights - * reserved. - * Copyright 2017-present Facebook, Inc. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <arch/io.h> -#include <arch/sysreg.h> -#include <delay.h> -#include <endian.h> -#include <soc/asm.h> -#include <soc/clock.h> -#include <soc/timer.h> -#include <stdint.h> -#include <timer.h> - -static uint64_t timer_raw_value(void) -{ - struct cn81xx_timer *timer = (void *)GTI_PF_BAR0; - - return read64(&timer->cc_cntcv); -} - -void timer_monotonic_get(struct mono_time *mt) -{ - mono_time_set_usecs(mt, timer_raw_value()); -} - -void init_timer(void) -{ - struct cn81xx_timer *gti = (struct cn81xx_timer *)GTI_PF_BAR0; - - /* Check if the counter was already setup */ - if (gti->cc_cntcr & GTI_CC_CNTCR_EN) - return; - - /* Configure GTI to tick at BDK_GTI_RATE */ - u64 sclk = thunderx_get_io_clock(); -#if 0 - /* - * FIXME(dhendrix): Had difficulty using reference code's way of - * setting up timer, the cntcv value didn't increment as expected. - */ - u64 inc = (BDK_GTI_RATE << 32) / sclk; - write32(>i->cc_cntrate, inc); -#endif - /* Let's try using sclk only */ - write32(>i->cc_cntfid0, sclk); /* TODO: ref. code didn't set cntfid0? */ - write32(>i->ctl_cntfrq, sclk); - write32(>i->cc_cntrate, ((1ULL << 32) * 1000000) / sclk); - - /* Enable the counter */ - setbits_le32(>i->cc_cntcr, GTI_CC_CNTCR_EN); - read32(>i->cc_cntcr); /* FIXME: is this needed? */ - - /* Enable the core timer */ - BDK_MSR(CNTFRQ_EL0, 100000000ull); /* Needed for Asim (FIXME: not needed for HW?) */ -#if 0 - bdk_ap_cntps_ctl_el1_t cntps_ctl_el1; - cntps_ctl_el1.u = 0; - cntps_ctl_el1.s.imask = 1; - cntps_ctl_el1.s.enable = 1; - BDK_MSR(CNTPS_CTL_EL1, cntps_ctl_el1.u); -#endif - u32 u = (CNTPS_CTL_EL1_IMASK | CNTPS_CTL_EL1_EN); - BDK_MSR(CNTPS_CTL_EL1, u); - return; -} diff --git a/src/soc/cavium/common/Makefile.inc b/src/soc/cavium/common/Makefile.inc index f51e13e..83e81a7 100644 --- a/src/soc/cavium/common/Makefile.inc +++ b/src/soc/cavium/common/Makefile.inc @@ -19,18 +19,21 @@ bootblock-y += twsi.c bootblock-y += clock.c bootblock-y += gpio.c +bootblock-y += timer.c
romstage-y += twsi.c romstage-y += clock.c romstage-y += gpio.c +romstage-y += timer.c
ramstage-y += twsi.c ramstage-y += clock.c ramstage-y += gpio.c +ramstage-y += timer.c
CPPFLAGS_common += -Isrc/soc/cavium/common/include
diff --git a/src/soc/cavium/common/include/soc/timer.h b/src/soc/cavium/common/include/soc/timer.h new file mode 100644 index 0000000..6d48831 --- /dev/null +++ b/src/soc/cavium/common/include/soc/timer.h @@ -0,0 +1,20 @@ +/* + * Copyright 2017-present Facebook, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOC_CAVIUM_CN81XX_TIMER_H__ +#define __SOC_CAVIUM_CN81XX_TIMER_H__ + +#include <inttypes.h> +#include <types.h> +#include <timer.h> + +/* Watchdog functions */ +void watchdog_set(const size_t index, unsigned int timeout_ms); +void watchdog_poke(const size_t index); +void watchdog_disable(const size_t index); +int watchdog_is_running(const size_t index); + +#endif /* __SOC_CAVIUM_CN81XX_TIMER_H__ */ diff --git a/src/soc/cavium/common/timer.c b/src/soc/cavium/common/timer.c new file mode 100644 index 0000000..ee8d639 --- /dev/null +++ b/src/soc/cavium/common/timer.c @@ -0,0 +1,218 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2003-2017 Cavium Inc. (support@cavium.com). All rights + * reserved. + * Copyright 2018-present Facebook, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch/io.h> +#include <console/console.h> +#include <inttypes.h> +#include <soc/clock.h> +#include <soc/timer.h> +#include <stdint.h> +#include <timer.h> +#include <soc/addressmap.h> +#include <assert.h> + +/* Global System Timers Unit (GTI) registers */ +struct cn81xx_timer { + u32 cc_cntcr; + u32 cc_cntsr; + u64 cc_cntcv; + u8 rsvd[0x10]; + u32 cc_cntfid0; + u32 cc_cntfid1; + u8 rsvd2[0x98]; + u32 cc_cntrate; + u32 cc_cntracc; + u64 cc_cntadd; + u64 cc_cntmb; + u64 cc_cntmbts; + u64 cc_cntmb_int; + u64 cc_cntmb_int_set; + u64 cc_cntmb_int_ena_clr; + u64 cc_cntmb_int_ena_set; + u64 cc_imp_ctl; + u8 skip[0x1fef8]; + u32 ctl_cntfrq; + u32 ctl_cntnsar; + u32 ctl_cnttidr; + u8 rsvd3[0x34]; + u32 ctl_cntacr0; + u8 skip2[0x1ffb8]; + u64 cwd_wdog[48]; /* Offset 0x40000 */ + u8 skip3[0xfe80]; + u64 cwd_poke[48]; /* Offset 0x50000 */ +}; + +check_member(cn81xx_timer, cc_imp_ctl, 0x100); +check_member(cn81xx_timer, ctl_cntacr0, 0x20040); +check_member(cn81xx_timer, cwd_wdog[0], 0x40000); +check_member(cn81xx_timer, cwd_poke[0], 0x50000); + + +#define GTI_CC_CNTCR_EN (1 << 0) +#define GTI_CC_CNTCR_HDBG (1 << 1) +#define GTI_CC_CNTCR_FCREQ (1 << 8) + +#define GTI_CC_CNTSR_DBGH (1 << 1) +#define GTI_CC_CNTSR_FCACK (1 << 8) + +#define GTI_CWD_WDOG_MODE_SHIFT 0 +#define GTI_CWD_WDOG_MODE_MASK 0x3 +#define GTI_CWD_WDOG_STATE_SHIFT 2 +#define GTI_CWD_WDOG_STATE_MASK 0x3 +#define GTI_CWD_WDOG_LEN_SHIFT 4 +#define GTI_CWD_WDOG_LEN_MASK 0xffff +#define GTI_CWD_WDOG_CNT_SHIFT 20 +#define GTI_CWD_WDOG_CNT_MASK 0xffffff +#define GTI_CWD_WDOC_DSTOP (1 << 44) +#define GTI_CWD_WDOC_GSTOP (1 << 45) + +static uint64_t timer_raw_value(void) +{ + struct cn81xx_timer *timer = (void *)GTI_PF_BAR0; + + return read64(&timer->cc_cntcv); +} + +/** + * Get GTI counter value. + * @param mt Structure to fill + */ +void timer_monotonic_get(struct mono_time *mt) +{ + mono_time_set_usecs(mt, timer_raw_value()); +} + +/** + * Init Global System Timers Unit (GTI). + * Configure timer to run at 1MHz tick-rate. + */ +void init_timer(void) +{ + struct cn81xx_timer *gti = (struct cn81xx_timer *)GTI_PF_BAR0; + + /* Check if the counter was already setup */ + if (gti->cc_cntcr & GTI_CC_CNTCR_EN) + return; + + u64 sclk = thunderx_get_io_clock(); + + /* Use coprocessor clock source */ + write32(>i->cc_imp_ctl, 0); + + /* Setup counter to operate at 1MHz */ + const size_t tickrate = 1000000; + write32(>i->cc_cntfid0, tickrate); + write32(>i->ctl_cntfrq, tickrate); + write32(>i->cc_cntrate, ((1ULL << 32) * tickrate) / sclk); + + /* Enable the counter */ + setbits_le32(>i->cc_cntcr, GTI_CC_CNTCR_EN); + + //u32 u = (CNTPS_CTL_EL1_IMASK | CNTPS_CTL_EL1_EN); + //BDK_MSR(CNTPS_CTL_EL1, u); +} + +/** + * Setup the watchdog to expire in timeout_ms milliseconds. When the watchdog + * expires, the chip three things happen: + * 1) Expire 1: interrupt that is ignored by the BDK + * 2) Expire 2: DEL3T interrupt, which is disabled and ignored + * 3) Expire 3: Soft reset of the chip + * + * Since we want a soft reset, we actually program the watchdog to expire at + * the timeout / 3. + * + * @param index Index of watchdog to configure + * @param timeout_ms Timeout in milliseconds. + */ +void watchdog_set(const size_t index, unsigned int timeout_ms) +{ + uint64_t sclk = thunderx_get_io_clock(); + uint64_t timeout_sclk = sclk * timeout_ms / 1000; + struct cn81xx_timer *timer = (struct cn81xx_timer *)GTI_PF_BAR0; + + assert(index < ARRAY_SIZE(timer->cwd_wdog)); + if (index >= ARRAY_SIZE(timer->cwd_wdog)) + return; + + /* + * Per comment above, we want the watchdog to expire at 3x the rate + * specified + */ + timeout_sclk /= 3; + /* Watchdog counts in 1024 cycle steps */ + uint64_t timeout_wdog = timeout_sclk >> 10; + /* We can only specify the upper 16 bits of a 24 bit value. Round up */ + timeout_wdog = (timeout_wdog + 0xff) >> 8; + /* If the timeout overflows the hardware limit, set max */ + if (timeout_wdog >= 0x10000) + timeout_wdog = 0xffff; + + printk(BIOS_DEBUG, "Watchdog: Set to expire %zu SCLK cycles\n", + timeout_wdog << 18); + clrsetbits_le64(&timer->cwd_wdog[index], + (GTI_CWD_WDOG_LEN_MASK << GTI_CWD_WDOG_LEN_SHIFT) | + (GTI_CWD_WDOG_MODE_MASK << GTI_CWD_WDOG_MODE_SHIFT), + (timeout_wdog << GTI_CWD_WDOG_LEN_SHIFT) | + (3 << GTI_CWD_WDOG_MODE_SHIFT)); +} + +/** + * Signal the watchdog that we are still running. + * + * @param index Index of watchdog to configure. + */ +void watchdog_poke(const size_t index) +{ + struct cn81xx_timer *timer = (struct cn81xx_timer *)GTI_PF_BAR0; + + assert(index < ARRAY_SIZE(timer->cwd_poke)); + if (index >= ARRAY_SIZE(timer->cwd_poke)) + return; + + write64(&timer->cwd_poke[0], 0); +} + +/** + * Disable the hardware watchdog + * + * @param index Index of watchdog to configure. + */ +void watchdog_disable(const size_t index) +{ + struct cn81xx_timer *timer = (struct cn81xx_timer *)GTI_PF_BAR0; + + assert(index < ARRAY_SIZE(timer->cwd_wdog)); + if (index >= ARRAY_SIZE(timer->cwd_wdog)) + return; + + write64(&timer->cwd_wdog[index], 0); + printk(BIOS_DEBUG, "Watchdog: Disabled\n"); +} + +/** + * Return true if the watchdog is configured and running + * + * @param index Index of watchdog to configure. + * + * @return Non-zero if watchdog is running. + */ +int watchdog_is_running(const size_t index) +{ + struct cn81xx_timer *timer = (struct cn81xx_timer *)GTI_PF_BAR0; + + assert(index < ARRAY_SIZE(timer->cwd_wdog)); + if (index >= ARRAY_SIZE(timer->cwd_wdog)) + return 0; + + uint64_t val = read64(&timer->cwd_wdog[index]); + + return !!(val & (GTI_CWD_WDOG_MODE_MASK << GTI_CWD_WDOG_MODE_SHIFT)); +} diff --git a/src/soc/cavium/common/wdt.c b/src/soc/cavium/common/wdt.c deleted file mode 100644 index 9b0f28f..0000000 --- a/src/soc/cavium/common/wdt.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2003-2017 Cavium Inc. (support@cavium.com). All rights - * reserved. - * Copyright 2018-present Facebook, Inc. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <arch/io.h> -#include <console/console.h> -#include <inttypes.h> -#include <soc/clock.h> -#include <soc/timer.h> - -/** - * Setup the watchdog to expire in timeout_ms milliseconds. When the watchdog - * expires, the chip three things happen: - * 1) Expire 1: interrupt that is ignored by the BDK - * 2) Expire 2: DEL3T interrupt, which is disabled and ignored - * 3) Expire 3: Soft reset of the chip - * - * Since we want a soft reset, we actually program the watchdog to expire at - * the timeout / 3. - * - * @param timeout_ms Timeout in milliseconds. If this is zero, the timeout is taken from the - * global configuration option BDK_BRD_CFG_WATCHDOG_TIMEOUT - */ -void watchdog_set(unsigned int timeout_ms) -{ - uint64_t sclk = thunderx_get_io_clock(); - uint64_t timeout_sclk = sclk * timeout_ms / 1000; - /* Per comment above, we want the watchdog to expire at 3x the rate specified */ - timeout_sclk /= 3; - /* Watchdog counts in 1024 cycle steps */ - uint64_t timeout_wdog = timeout_sclk >> 10; - /* We can only specify the upper 16 bits of a 24 bit value. Round up */ - timeout_wdog = (timeout_wdog + 0xff) >> 8; - /* If the timeout overflows the hardware limit, set max */ - if (timeout_wdog >= 0x10000) - timeout_wdog = 0xffff; - - printk(BIOS_DEBUG, "Watchdog: Set to expire %llu SCLK cycles\n", timeout_wdog << 18); - struct cn81xx_timer *timer = (struct cn81xx_timer *)GTI_PF_BAR0; - clrsetbits_le64(&timer->cwd_wdog0, - (GTI_CWD_WDOG_LEN_MASK << GTI_CWD_WDOG_LEN_SHIFT) | - (GTI_CWD_WDOG_MODE_MASK << GTI_CWD_WDOG_MODE_SHIFT), - (timeout_wdog << GTI_CWD_WDOG_LEN_SHIFT) | - (3 << GTI_CWD_WDOG_MODE_SHIFT)); -} - -/** - * Signal the watchdog that we are still running - */ -void watchdog_poke(void) -{ - struct cn81xx_timer *timer = (struct cn81xx_timer *)GTI_PF_BAR0; - write64(&timer->cwd_poke0, 0); -// BDK_CSR_WRITE(bdk_numa_local(), BDK_GTI_CWD_POKEX(bdk_get_core_num()), 0); -} - -/** - * Disable the hardware watchdog - */ -void watchdog_disable(void) -{ - struct cn81xx_timer *timer = (struct cn81xx_timer *)GTI_PF_BAR0; - write64(&timer->cwd_wdog0, 0); -// BDK_CSR_WRITE(bdk_numa_local(), BDK_GTI_CWD_WDOGX(bdk_get_core_num()), 0); -// BDK_TRACE(INIT, "Watchdog: Disabled\n"); - printk(BIOS_DEBUG, "Watchdog: Disabled\n"); -} - -/** - * Return true if the watchdog is configured and running - * - * @return Non-zero if watchdog is running - */ -int watchdog_is_running(void) -{ - struct cn81xx_timer *timer = (struct cn81xx_timer *)GTI_PF_BAR0; - uint64_t val = read64(&timer->cwd_wdog0); - - return !!(val & (GTI_CWD_WDOG_MODE_MASK << GTI_CWD_WDOG_MODE_SHIFT)); -// BDK_CSR_INIT(wdog, bdk_numa_local(), BDK_GTI_CWD_WDOGX(bdk_get_core_num())); - // return wdog.s.mode != 0; -}
-
Patrick Rudolph (Code Review)