Matthew Garrett has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34458 )
Change subject: soc/intel/skylake: Enable Energy/Performance Bias control ......................................................................
soc/intel/skylake: Enable Energy/Performance Bias control
Bit 18 of MSR_POWER_CTL is documented as reserved, but we're setting it on Haswell in order to enable EPB. It seems to work on SKL/KBL as well, so do it there too.
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: I83da1a57a04dac206cc67f2c256d0c102965abc2 --- M src/soc/intel/skylake/cpu.c 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/34458/1
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 5f4ce87..2fd01b4 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -313,6 +313,7 @@
msr = rdmsr(MSR_POWER_CTL); msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ + msr.lo |= (1 << 18); /* Enable Energy/Performance Bias control */ msr.lo &= ~POWER_CTL_C1E_MASK; /* Disable C1E */ msr.lo |= (1 << 23); /* Lock it */ wrmsr(MSR_POWER_CTL, msr);
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34458 )
Change subject: soc/intel/skylake: Enable Energy/Performance Bias control ......................................................................
Patch Set 1: Code-Review+2
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34458 )
Change subject: soc/intel/skylake: Enable Energy/Performance Bias control ......................................................................
soc/intel/skylake: Enable Energy/Performance Bias control
Bit 18 of MSR_POWER_CTL is documented as reserved, but we're setting it on Haswell in order to enable EPB. It seems to work on SKL/KBL as well, so do it there too.
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: I83da1a57a04dac206cc67f2c256d0c102965abc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34458 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/skylake/cpu.c 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 5f4ce87..2fd01b4 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -313,6 +313,7 @@
msr = rdmsr(MSR_POWER_CTL); msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ + msr.lo |= (1 << 18); /* Enable Energy/Performance Bias control */ msr.lo &= ~POWER_CTL_C1E_MASK; /* Disable C1E */ msr.lo |= (1 << 23); /* Lock it */ wrmsr(MSR_POWER_CTL, msr);
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Angel Pons (Code Review) -
Martin Roth (Code Review)
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Matthew Garrett (Code Review)