Change in coreboot[master]: soc/amd/picasso/acpi/sb_fch: add SPI controller

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47826 )

Change subject: soc/amd/picasso/acpi/sb_fch: add SPI controller
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soc/amd/picasso/acpi/sb_fch: add SPI controller

Change-Id: If1bc33dd264327f9119e1019700510ba9acca810
Signed-off-by: Felix Held 
---
M src/soc/amd/picasso/acpi/sb_fch.asl
1 file changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/47826/1

diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl
index 6cbfc5f..5ab363d 100644
--- a/src/soc/amd/picasso/acpi/sb_fch.asl
+++ b/src/soc/amd/picasso/acpi/sb_fch.asl
@@ -19,6 +19,21 @@
    }
 }

+Device (SPI0)
+{
+	Name (_HID, "AMDI0061")
+	Name (_UID, 0)
+	Name (_CRS, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, SPI_BASE_ADDRESS, 0x100)
+	})
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0f)
+	}
+}
+
 Device (GPIO)
 {
    Name (_HID, GPIO_DEVICE_NAME)

[Martin Roth (Code Review)]

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47826 )

Change subject: soc/amd/picasso/acpi/sb_fch: add SPI controller
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Patch Set 1:

Unfortunately, the OS can't really use the spi controller for anything because there's no hardware arbitration.  Any reads to the SPI ROM's memory address will automatically get sent out over the spi bus to the Firmware ROM, messing up any transactions if there were another device on the SPI bus.

Because of that, I think it's better just not to even tell the OS about the spi controller.

[Felix Held (Code Review)]

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47826 )

Change subject: soc/amd/picasso/acpi/sb_fch: add SPI controller
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Patch Set 1: Code-Review-1
> Patch Set 1:
>
> Unfortunately, the OS can't really use the spi controller for anything because there's no hardware arbitration.  Any reads to the SPI ROM's memory address will automatically get sent out over the spi bus to the Firmware ROM, messing up any transactions if there were another device on the SPI bus.
>
> Because of that, I think it's better just not to even tell the OS about the spi controller.

oh, you might have a point there. I'll add a -1, so that it won't accidentally get merged for now; not sure when I'll get around to have a close look into this

[Felix Held (Code Review)]

Felix Held has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/47826 )

Change subject: soc/amd/picasso/acpi/sb_fch: add SPI controller
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Abandoned

i'll abandon this for now; if we find a proper solution, i can revive this patch