Change in ...coreboot[master]: soc/intel/icelake: Correct the GPE DWx mapping for GPIO groups

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32508 )

Change subject: soc/intel/icelake: Correct the GPE DWx mapping for GPIO groups
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soc/intel/icelake: Correct the GPE DWx mapping for GPIO groups

This implementation corrects the GPE DWx mapping for GPIO groups.
The assignments is done in GPIO MISCFG register for all GPIO communities.
And configures the which GPIO communities get register as Tier1.

Change-Id: I9c306d46e5194944def26c24cdb95f5ebada42b8
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32508
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Rizwan Qureshi 
---
M src/soc/intel/icelake/include/soc/gpio_soc_defs.h
1 file changed, 12 insertions(+), 11 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Rizwan Qureshi: Looks good to me, approved

diff --git a/src/soc/intel/icelake/include/soc/gpio_soc_defs.h b/src/soc/intel/icelake/include/soc/gpio_soc_defs.h
index e3eaf62..5a27a15 100644
--- a/src/soc/intel/icelake/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/icelake/include/soc/gpio_soc_defs.h
@@ -21,17 +21,18 @@
  * The GPIO groups are accessed through register blocks called
  * communities.
  */
-#define GPP_G			0
-#define GPP_B			1
-#define GPP_A			2
-#define GPP_H			3
-#define GPP_D			4
-#define GPP_F			5
-#define GPD			6
-#define GPP_C			7
-#define GPP_E			8
-#define GPP_R			9
-#define GPP_S			0xA
+#define GPP_G			0x0
+#define GPP_B			0x1
+#define GPP_A			0x2
+#define GPP_R			0x3
+#define GPP_S			0x4
+#define GPD			0x5
+#define GPP_H			0x6
+#define GPP_D			0x7
+#define GPP_F			0x8
+#define GPP_VGPIO		0x9
+#define GPP_C			0xA
+#define GPP_E			0xB

#define GPIO_NUM_GROUPS		11
 #define GPIO_MAX_NUM_PER_GROUP	24