Change in coreboot[master]: soc/intel/skylake: [WIP] enable microcode update

[Rizwan Qureshi (Code Review)]

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/27370

Change subject: soc/intel/skylake: [WIP] enable microcode update
......................................................................

soc/intel/skylake: [WIP] enable microcode update

Change-Id: Ic492a8600c7400055ce4b950408f33c6463e0f92
Signed-off-by: Rizwan Qureshi 
---
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/romstage/romstage_fsp20.c
2 files changed, 7 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/27370/1

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 3e0158b..fdf78f5 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -74,6 +74,8 @@
    select TSC_MONOTONIC_TIMER
    select TSC_SYNC_MFENCE
    select UDELAY_TSC
+	select INTEL_HAS_TOP_SWAP
+	select INTEL_ADD_TOP_SWAP_BOOTBLOCK

config MAINBOARD_USES_FSP2_0
    bool
@@ -348,5 +350,7 @@
 config IFD_CHIPSET
    string
    default "sklkbl"
-
+config INTEL_TOP_SWAP_FIT_ENTRY
+	string
+	default "RW_UCODE_STAGED"
 endif
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 64f9d7d..d4d27b1 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -38,6 +38,7 @@
 #include <string.h>
 #include <timestamp.h>
 #include <security/vboot/vboot_common.h>
+#include <soc/ucode_update.h>

#define FSP_SMBIOS_MEMORY_INFO_GUID	\
 {	\
@@ -142,6 +143,7 @@
    struct chipset_power_state *ps;

console_init();
+	check_and_update_ucode();

/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
    systemagent_early_init();