[S] Change in coreboot[master]: soc/amd/common/data_fabric/domain: read IO decode windows from registers

[Felix Held (Code Review)]

Attention is currently required from: Felix Held, Jason Glenesk, Martin Roth, Matt DeVillier, Raul Rangel.

Hello Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/76960?usp=email

to look at the new patch set (#6).

Change subject: soc/amd/common/data_fabric/domain: read IO decode windows from registers
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soc/amd/common/data_fabric/domain: read IO decode windows from registers

Before add_io_regions only reported one fixed IO range to the resource
allocator that covered the whole IO range from 0x0000 to 0xffff. Instead
read the data fabric IO space decode base and limit address register
pairs to get the actual IO port decoding from the data fabric registers.
This will also help with adding support for multiple PCI root domains to
the common data fabric domain code so that Genoa can use it. In that
case each PCI root domain will only decode a part of the whole IO port
range.

Beware that the data fabric IO base and limit fields can contain values
that correspond to IO port addresses far outside of the addressable IO
port range. In case of Picasso, the IO limit read from the only enabled
DF IO range register would be 0x1ffffff after converting the raw data to
an IO port address. To not give the resource allocator wrong constraints
make sure that the IO limit we report will be at maximum 0xffff.

TEST=On Mandolin (Picasso) and Birman (Phoenix) the full range of IO
port addresses still gets reported as a domain IO resource producer like
before the patch:

DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done

Signed-off-by: Felix Held 
Tested-by: Fred Reitberger 
Change-Id: I087d96f7bdaae0d7b53089f6abaf0500a4b064e9
---
M src/soc/amd/common/block/data_fabric/domain.c
1 file changed, 33 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/76960/6