[M] Change in coreboot[master]: drivers/intel/fsp2_0: Update MRC cache in ramstage

[Reka Norman (Code Review)]

Attention is currently required from: Kangheui Won, Tim Wawrzynczak, Paul Menzel, Julius Werner, Angel Pons, Sridhar Siricilla, Arthur Heymans, Eric Lai, Ronak Kanabar, Andrey Petrov.

Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67669 )

Change subject: drivers/intel/fsp2_0: Update MRC cache in ramstage
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Patch Set 2:

(3 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/67669/comment/c72b0aa3_3d367274 
PS1, Line 18:
> Since mrc_cache_find_current() will still compare against the version in the header, we need to get  […]

This won't work since FSP_INFO_HOB is not available on every FSP 2 platform. It was added between Apollo Lake and Comet Lake. Intel also confirmed in b/248459174 that there's no other way to get the image_revision from the HOBs.

Julius, are you alright with adding it to cbmem?

Patchset:

PS1:
> > Sure, I'm happy with that. […]

Fair enough. I've changed the boot state entry to ensure save_mrc_data() happens before ramstage_cse_fw_sync(), which should cover ADL onwards.

File src/drivers/intel/fsp2_0/memory_init.c:

https://review.coreboot.org/c/coreboot/+/67669/comment/852a4d71_0b2c12fb 
PS1, Line 56: 	if (CONFIG(CACHE_MRC_SETTINGS)) {
> I see, SG!

Done