Attention is currently required from: Furquan Shaikh, Neill Corlett. Joe Tessler has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50101 )
Change subject: hatch: Modify genesis PcieClkSrc settings ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50101/comment/d7c98516_acfb8fc0 PS2, Line 9: to work around issue with Longsys SSD
I think it would be good to provide some context as to why the change is being made. […]
This was required to support a specific SSD module on the M.2 slot that uses PCIe slots 11 & 12 as advertised for "NVMe hybrid storage devices". Apparently my way of registering the clock sources only worked on the SSD module I had on hand.
That being said, I'm completely stumped as to why this patch fixes the issue. I would've expected just `register "PcieRpEnable[11]" = "1"` change, but I don't have access to the hardware to verify it myself.
Do you think this is sufficient / should be added to the commit message?
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Joe Tessler (Code Review)