Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44063 )
Change subject: vc/amd/fsp/picasso: document DXIO lane number mapping ......................................................................
vc/amd/fsp/picasso: document DXIO lane number mapping
Haven't found official documentation for the DXIO lane mapping on Pollock, so I haven't added a table for that yet.
Change-Id: I53aac0aeba8466ae456f0f935114b587b64eeeaa Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/vendorcode/amd/fsp/picasso/platform_descriptors.h 1 file changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/44063/1
diff --git a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h index 2faa0ab..b99980f 100644 --- a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h +++ b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h @@ -113,6 +113,28 @@ * Picasso DXIO Descriptor: Used for assigning lanes to PCIe/SATA/XGBE engines, configure * bifurcation and other settings. Beware that the lane numbers in here are the logical and not * the physical lane numbers! + * + * Picasso DXIO lane mapping: + * + * physical | logical | protocol + * ---------|---------|----------- + * GFX[7:0] | [15:8] | PCIe + * GPP[3:0] | [7:4] | PCIe + * GPP[5:4] | [1:0] | PCIe, XGBE + * GPP[7:6] | [3:2] | PCIe, SATA + * + * Dali has less DXIO connectivity than Picasso: + * + * physical | logical | protocol + * ---------|---------|----------- + * GFX[3:0] | [11:8] | PCIe + * GPP[1:0] | [5:4] | PCIe + * GPP[5:4] | [1:0] | PCIe, XGBE + * GPP[7:6] | [3:2] | SATA + * + * Pollock has even less DXIO lanes and the mapping of GPP lane numbers to the logical lane + * numbers differs to Picasso/Dali. Only logical lanes [1:0] and [5:4] are present and they + * only support PCIe. */ typedef struct __packed { uint8_t engine_type;
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44063 )
Change subject: vc/amd/fsp/picasso: document DXIO lane number mapping ......................................................................
Patch Set 1: Code-Review+2
Hello Jason Glenesk, build bot (Jenkins), Raul Rangel, Furquan Shaikh, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44063
to look at the new patch set (#2).
Change subject: vc/amd/fsp/picasso: document DXIO lane number mapping ......................................................................
vc/amd/fsp/picasso: document DXIO lane number mapping
Haven't found the official documentation for the DXIO lane mapping on Pollock, so I had to guess that from the working configurations used in google/dalboz and amd/cereme.
Change-Id: I53aac0aeba8466ae456f0f935114b587b64eeeaa Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/vendorcode/amd/fsp/picasso/platform_descriptors.h 1 file changed, 26 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/44063/2
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44063 )
Change subject: vc/amd/fsp/picasso: document DXIO lane number mapping ......................................................................
Patch Set 2: Code-Review+2
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44063 )
Change subject: vc/amd/fsp/picasso: document DXIO lane number mapping ......................................................................
Patch Set 2: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/44063/2/src/vendorcode/amd/fsp/pica... File src/vendorcode/amd/fsp/picasso/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/44063/2/src/vendorcode/amd/fsp/pica... PS2, Line 141: * GPP[3:2] | [5:4] | PCIe It would be great to add the pci bridge device and funciton to this because we empirically have a mismatch. e.g. 00:01.7 shows up on pollock despite PPR suggesting otherwise.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44063 )
Change subject: vc/amd/fsp/picasso: document DXIO lane number mapping ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/44063/2/src/vendorcode/amd/fsp/pica... File src/vendorcode/amd/fsp/picasso/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/44063/2/src/vendorcode/amd/fsp/pica... PS2, Line 124: * GPP[7:6] | [3:2] | PCIe, SATA What's the difference between GFX and GPP physical lanes?
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44063 )
Change subject: vc/amd/fsp/picasso: document DXIO lane number mapping ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44063/2/src/vendorcode/amd/fsp/pica... File src/vendorcode/amd/fsp/picasso/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/44063/2/src/vendorcode/amd/fsp/pica... PS2, Line 141: * GPP[3:2] | [5:4] | PCIe
It would be great to add the pci bridge device and funciton to this because we empirically have a mi […]
I'll have a look; that'll be a follow-up patch though. The assignment of the PCIe engines to lanes isn't fixed, but has some constraints that have to be met.
Looked for some more documentation on Pollock yesterday, but didn't find that much new info.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44063 )
Change subject: vc/amd/fsp/picasso: document DXIO lane number mapping ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44063/2/src/vendorcode/amd/fsp/pica... File src/vendorcode/amd/fsp/picasso/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/44063/2/src/vendorcode/amd/fsp/pica... PS2, Line 124: * GPP[7:6] | [3:2] | PCIe, SATA
What's the difference between GFX and GPP physical lanes?
The lanes themselves are the same; the names are the ones that are used in the schematics and on the package pins/balls. GFX lanes are mostly meant to be used for GPU connectivity, but they can also be used to connect to one or two non-GPU devices.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44063 )
Change subject: vc/amd/fsp/picasso: document DXIO lane number mapping ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44063/2/src/vendorcode/amd/fsp/pica... File src/vendorcode/amd/fsp/picasso/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/44063/2/src/vendorcode/amd/fsp/pica... PS2, Line 124: * GPP[7:6] | [3:2] | PCIe, SATA
The lanes themselves are the same; the names are the ones that are used in the schematics and on the […]
Ah. What does GPP mean? (If possible to explain)
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44063 )
Change subject: vc/amd/fsp/picasso: document DXIO lane number mapping ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44063/2/src/vendorcode/amd/fsp/pica... File src/vendorcode/amd/fsp/picasso/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/44063/2/src/vendorcode/amd/fsp/pica... PS2, Line 124: * GPP[7:6] | [3:2] | PCIe, SATA
Ah. […]
probably general purpose port
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44063 )
Change subject: vc/amd/fsp/picasso: document DXIO lane number mapping ......................................................................
Patch Set 3: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44063 )
Change subject: vc/amd/fsp/picasso: document DXIO lane number mapping ......................................................................
vc/amd/fsp/picasso: document DXIO lane number mapping
Haven't found the official documentation for the DXIO lane mapping on Pollock, so I had to guess that from the working configurations used in google/dalboz and amd/cereme.
Change-Id: I53aac0aeba8466ae456f0f935114b587b64eeeaa Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/44063 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Raul Rangel rrangel@chromium.org Reviewed-by: Aaron Durbin adurbin@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/vendorcode/amd/fsp/picasso/platform_descriptors.h 1 file changed, 26 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Raul Rangel: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h index 2faa0ab..9c0e3e9 100644 --- a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h +++ b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h @@ -113,6 +113,32 @@ * Picasso DXIO Descriptor: Used for assigning lanes to PCIe/SATA/XGBE engines, configure * bifurcation and other settings. Beware that the lane numbers in here are the logical and not * the physical lane numbers! + * + * Picasso DXIO lane mapping: + * + * physical | logical | protocol + * ---------|---------|----------- + * GFX[7:0] | [15:8] | PCIe + * GPP[3:0] | [7:4] | PCIe + * GPP[5:4] | [1:0] | PCIe, XGBE + * GPP[7:6] | [3:2] | PCIe, SATA + * + * Dali has less DXIO connectivity than Picasso: + * + * physical | logical | protocol + * ---------|---------|----------- + * GFX[3:0] | [11:8] | PCIe + * GPP[1:0] | [5:4] | PCIe + * GPP[5:4] | [1:0] | PCIe, XGBE + * GPP[7:6] | [3:2] | SATA + * + * Pollock has even less DXIO lanes and the mapping of GPP lane numbers to the logical lane + * numbers differs to Picasso/Dali: + * + * physical | logical | protocol + * ---------|---------|---------- + * GPP[1:0] | [1:0] | PCIe + * GPP[3:2] | [5:4] | PCIe */ typedef struct __packed { uint8_t engine_type;
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Aaron Durbin (Code Review) -
Angel Pons (Code Review)
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Felix Held (Code Review)
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Raul Rangel (Code Review)