[S] Change in coreboot[main]: mb/google/fatcat: Update flash layout

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85497?usp=email )

Change subject: mb/google/fatcat: Update flash layout
......................................................................

mb/google/fatcat: Update flash layout

This patch updates the flash layout for Fatcat variants to ensure
the flash layout is in alignment with the previous generation CrOS
devices like Rex.

SI_ALL: 9MB -> 8MB
SI_BIOS: 23MB -> 24MB

BUG=b:382247229
TEST=Able to build and boot google/fatcat.

Change-Id: I716fae09dee0c05b8b840dc80647d7959aa03a50
Signed-off-by: Subrata Banik 
---
M src/mainboard/google/fatcat/chromeos-debug-fsp.fmd
M src/mainboard/google/fatcat/chromeos.fmd
2 files changed, 24 insertions(+), 24 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/85497/1

diff --git a/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd b/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd
index 8d41977..0e1e636 100644
--- a/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd
+++ b/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd
@@ -1,23 +1,14 @@
 FLASH 32M {
-	SI_ALL 9M {
+	SI_ALL 8M {
    	SI_DESC 16K
    	SI_ME
    }
-	SI_BIOS 23M {
+	SI_BIOS 24M {
    	RW_SECTION_A 7680K {
    		VBLOCK_A 8K
    		FW_MAIN_A(CBFS)
    		RW_FWID_A 64
    	}
-		# This section starts at the 16M boundary in SPI flash.
-		# PTL does not support a region crossing this boundary,
-		# because the SPI flash is memory-mapped into two non-
-		# contiguous windows.
-		RW_SECTION_B 7680K {
-			VBLOCK_B 8K
-			FW_MAIN_B(CBFS)
-			RW_FWID_B 64
-		}
    	RW_MISC 1M {
    		UNIFIED_MRC_CACHE(PRESERVE) 128K {
    			RECOVERY_MRC_CACHE 64K
@@ -31,8 +22,17 @@
    		RW_VPD(PRESERVE) 8K
    		RW_NVRAM(PRESERVE) 24K
    	}
+		# This section starts at the 16M boundary in SPI flash.
+		# PTL does not support a region crossing this boundary,
+		# because the SPI flash is memory-mapped into two non-
+		# contiguous windows.
+		RW_SECTION_B 7680K {
+			VBLOCK_B 8K
+			FW_MAIN_B(CBFS)
+			RW_FWID_B 64
+		}
    	RW_LEGACY(CBFS) 1M
-		RW_UNUSED 2M
+		RW_UNUSED 3M
    	# Make WP_RO region align with SPI vendor
    	# memory protected range specification.
    	WP_RO 4M {
diff --git a/src/mainboard/google/fatcat/chromeos.fmd b/src/mainboard/google/fatcat/chromeos.fmd
index 4b42403..ca29bbc 100644
--- a/src/mainboard/google/fatcat/chromeos.fmd
+++ b/src/mainboard/google/fatcat/chromeos.fmd
@@ -1,23 +1,14 @@
 FLASH 32M {
-	SI_ALL 9M {
+	SI_ALL 8M {
    	SI_DESC 16K
    	SI_ME
    }
-	SI_BIOS 23M {
+	SI_BIOS 24M {
    	RW_SECTION_A 7M {
    		VBLOCK_A 8K
    		FW_MAIN_A(CBFS)
    		RW_FWID_A 64
    	}
-		# This section starts at the 16M boundary in SPI flash.
-		# PTL does not support a region crossing this boundary,
-		# because the SPI flash is memory-mapped into two non-
-		# contiguous windows.
-		RW_SECTION_B 7M {
-			VBLOCK_B 8K
-			FW_MAIN_B(CBFS)
-			RW_FWID_B 64
-		}
    	RW_MISC 1M {
    		UNIFIED_MRC_CACHE(PRESERVE) 128K {
    			RECOVERY_MRC_CACHE 64K
@@ -31,8 +22,17 @@
    		RW_VPD(PRESERVE) 8K
    		RW_NVRAM(PRESERVE) 24K
    	}
+		# This section starts at the 16M boundary in SPI flash.
+		# PTL does not support a region crossing this boundary,
+		# because the SPI flash is memory-mapped into two non-
+		# contiguous windows.
+		RW_SECTION_B 7M {
+			VBLOCK_B 8K
+			FW_MAIN_B(CBFS)
+			RW_FWID_B 64
+		}
    	RW_LEGACY(CBFS) 1M
-		RW_UNUSED 3M
+		RW_UNUSED 4M
    	# Make WP_RO region align with SPI vendor
    	# memory protected range specification.
    	WP_RO 4M {