[S] Change in coreboot[master]: mb/google/dedede/variants/sasukette: Disable PCIE RP8 and CLKSRC4

[Eric Lai (Code Review)]

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69848 )

Change subject: mb/google/dedede/variants/sasukette: Disable PCIE RP8 and CLKSRC4
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mb/google/dedede/variants/sasukette: Disable PCIE RP8 and CLKSRC4

This change disables unused PCIE RP8 and CLKSRC4. Without this change
sasukette cannot enter into s0ix properly.

BUG=b:259891452
TEST=Build and verified in sasukette

Change-Id: I61bcefa128d4f39613a760b647048f9e19e262c2
Signed-off-by: Rui Zhou 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69848
Tested-by: build bot (Jenkins) 
Reviewed-by: zanxi chen 
Reviewed-by: Henry Sun 
Reviewed-by: Maulik Vaghela 
Reviewed-by: Dtrain Hsu 
Reviewed-by: Eric Lai 
---
M src/mainboard/google/dedede/variants/sasukette/overridetree.cb
1 file changed, 27 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Maulik Vaghela: Looks good to me, approved
  Dtrain Hsu: Looks good to me, approved
  Henry Sun: Looks good to me, but someone else must approve
  zanxi chen: Looks good to me, but someone else must approve
  Eric Lai: Looks good to me, approved

diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb
index 1cda193..43a68db 100644
--- a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb
@@ -8,6 +8,10 @@
 end

chip soc/intel/jasperlake
+	# Disable PCIe Root Port 8 (index 7)
+	register "PcieRpEnable[7]" = "0"
+	# Disable PCIe Clock Source 4 (index 3)
+	register "PcieClkSrcUsage[3]" = "0xff"

# Intel Common SoC Config
    #+-------------------+---------------------------+