Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84378?usp=email )
Change subject: soc/amd/glinda: Update gpp bridge naming scheme ......................................................................
soc/amd/glinda: Update gpp bridge naming scheme
This patch updates the naming scheme used for the GPP bridges. The naming scheme now matches what we also have on phoenix.
Change-Id: I9f740d75a3561dba2ed65acb16bb4259f632307d Signed-off-by: Maximilian Brune maximilian.brune@9elements.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/84378 Reviewed-by: Felix Held felix-coreboot@felixheld.de Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Marshall Dawson marshalldawson3rd@gmail.com --- M src/mainboard/amd/birman/devicetree_glinda.cb M src/mainboard/amd/birman_plus/devicetree_glinda.cb M src/soc/amd/glinda/chipset.cb 3 files changed, 15 insertions(+), 12 deletions(-)
Approvals: Marshall Dawson: Looks good to me, approved build bot (Jenkins): Verified Felix Held: Looks good to me, approved
diff --git a/src/mainboard/amd/birman/devicetree_glinda.cb b/src/mainboard/amd/birman/devicetree_glinda.cb index f1a99f6..2e06f2b 100644 --- a/src/mainboard/amd/birman/devicetree_glinda.cb +++ b/src/mainboard/amd/birman/devicetree_glinda.cb @@ -158,9 +158,10 @@
device domain 0 on device ref iommu on end - device ref gpp_bridge_0 on end # GBE - device ref gpp_bridge_1 on end # WIFI - device ref gpp_bridge_2 on end # NVMe SSD + device ref gpp_bridge_2_1 on end # GBE + device ref gpp_bridge_2_2 on end # WIFI + device ref gpp_bridge_2_3 on end # NVMe SSD + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) diff --git a/src/mainboard/amd/birman_plus/devicetree_glinda.cb b/src/mainboard/amd/birman_plus/devicetree_glinda.cb index 1df02ed..e867f01 100644 --- a/src/mainboard/amd/birman_plus/devicetree_glinda.cb +++ b/src/mainboard/amd/birman_plus/devicetree_glinda.cb @@ -158,9 +158,9 @@
device domain 0 on device ref iommu on end - device ref gpp_bridge_0 on end # GBE - device ref gpp_bridge_1 on end # WIFI - device ref gpp_bridge_2 on end # NVMe SSD + device ref gpp_bridge_2_1 on end # GBE + device ref gpp_bridge_2_2 on end # WIFI + device ref gpp_bridge_2_3 on end # NVMe SSD device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) diff --git a/src/soc/amd/glinda/chipset.cb b/src/soc/amd/glinda/chipset.cb index 6e23c2d..f328797 100644 --- a/src/soc/amd/glinda/chipset.cb +++ b/src/soc/amd/glinda/chipset.cb @@ -14,13 +14,15 @@ device pci 01.2 alias usb4_pcie_bridge_1 off end device pci 01.3 alias usb4_pcie_bridge_2 off end
+ # The PCIe GPP aliases in this SoC match the device and function numbers device pci 02.0 on end # Dummy device function, do not disable - device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end - device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end - device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end - device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end - device pci 02.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end - device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end + device pci 02.1 alias gpp_bridge_2_1 off ops amd_external_pcie_gpp_ops end + device pci 02.2 alias gpp_bridge_2_2 off ops amd_external_pcie_gpp_ops end + device pci 02.3 alias gpp_bridge_2_3 off ops amd_external_pcie_gpp_ops end + device pci 02.4 alias gpp_bridge_2_4 off ops amd_external_pcie_gpp_ops end + device pci 02.5 alias gpp_bridge_2_5 off ops amd_external_pcie_gpp_ops end + device pci 02.6 alias gpp_bridge_2_6 off ops amd_external_pcie_gpp_ops end + device pci 03.0 on end # Dummy device function, do not disable device pci 03.1 alias gpp_bridge_3_1 off ops amd_external_pcie_gpp_ops end device pci 03.2 alias gpp_bridge_3_2 off ops amd_external_pcie_gpp_ops end
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Martin L Roth (Code Review)