[S] Change in coreboot[master]: sb/intel/i82801gx/early_init.c: Fix write_pmbase16() parameters

[Elyes Haouas (Code Review)]

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69979 )

Change subject: sb/intel/i82801gx/early_init.c: Fix write_pmbase16() parameters
......................................................................

sb/intel/i82801gx/early_init.c: Fix write_pmbase16() parameters

Change-Id: I635ef5c5b70123d06913023a0e91724285488e4f
Signed-off-by: Elyes Haouas 
---
M src/southbridge/intel/i82801gx/early_init.c
1 file changed, 13 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/69979/1

diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c
index dda5c00..970f730 100644
--- a/src/southbridge/intel/i82801gx/early_init.c
+++ b/src/southbridge/intel/i82801gx/early_init.c
@@ -71,9 +71,9 @@

printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
    RCBA32(GCS) = RCBA32(GCS) | (1 << 5);	/* No reset */
-	write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, TCO_TMR_HLT);
-	write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT);
-	write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, SECOND_TO_STS);
+	write_pmbase16(TCO1_CNT, TCO_TMR_HLT);
+	write_pmbase16(TCO1_STS, TCO1_TIMEOUT);
+	write_pmbase16(TCO2_STS, SECOND_TO_STS);
    printk(BIOS_DEBUG, " done.\n");

/* program secondary mlt XXX byte? */