Change in coreboot[master]: soc/amd/common: Handle power resume after power failure

[Raul Rangel (Code Review)]

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Martin Roth, Marshall Dawson, Karthik Ramasubramanian, Felix Held.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51924 )

Change subject: soc/amd/common: Handle power resume after power failure
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Patch Set 2: Code-Review+1

(1 comment)

File src/soc/amd/common/block/pm/pmlib.c:

https://review.coreboot.org/c/coreboot/+/51924/comment/aa8c9735_931ab825 
PS2, Line 42: PM_RTC_SHADOW_REG
Writing to these four bits will set the value onto bits [7:4]. Software
should always set bit 2 = 1.
Should we set bit 2? The reset value is 0 according to the PPR. I think bit 2 is powerstate.