Change in coreboot[master]: soc/intel/common: Don't clear GPE status register

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/28337

Change subject: soc/intel/common: Don't clear GPE status register
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soc/intel/common: Don't clear GPE status register

As per EDS definition for GPE Status register is RW/1C/V, hence
writting mask bit into GPE status will force clear GPE status bit.

This will lead into device side "IRQ timeout" problem as soc code
might relying on GPE status read to know the interrupt status.

TEST=Don't see IRQ timeout issue for TPM.

Change-Id: I27fabb3612251fd8d04f58c05ff9fb2a42ad64b3
Signed-off-by: Subrata Banik 
---
M src/soc/intel/common/block/pmc/pmclib.c
1 file changed, 3 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/28337/1

diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
index 339e674..7f106f4 100644
--- a/src/soc/intel/common/block/pmc/pmclib.c
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -460,7 +460,7 @@
    return acpi_sleep_from_pm1(pmc_read_pm1_control()) == ACPI_S3;
 }

-/* Read and clear GPE status (defined in arch/acpi.h) */
+/* Read GPE status (defined in arch/acpi.h) */
 int acpi_get_gpe(int gpe)
 {
    int bank;
@@ -474,17 +474,15 @@
    bank = gpe / 32;
    mask = 1 << (gpe % 32);

-	/* Wait up to 1ms for GPE status to clear */
+	/* Wait up to 1ms for GPE status to trigger */
    stopwatch_init_msecs_expire(&sw, 1);
    do {
    	if (stopwatch_expired(&sw))
    		return rc;

sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank));
-		if (sts & mask) {
-			outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank));
+		if (sts & mask)
    		rc = 1;
-		}
    } while (sts & mask);

return rc;