Change in coreboot[master]: device/pci_device.c: Improve pci_bridge_route() readability

[Arthur Heymans (Code Review)]

Attention is currently required from: Arthur Heymans.
Hello Arthur Heymans,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/59131

to review the following change.

Change subject: device/pci_device.c: Improve pci_bridge_route() readability
......................................................................

device/pci_device.c: Improve pci_bridge_route() readability

Both the secondary and subordinate bus numbers are configured in this
function but it's not easy to search for in the tree as the PCI writes
are hidden inside a bigger write to 'PCI_PRIMARY_BUS'. Using an
union/struct removes the need to juggle with bitwise operations.

Change-Id: I3bafd6a2e1d3a0b8d1d43997868a787ce3940ca9
Signed-off-by: Arthur Heymans 
---
M src/device/pci_device.c
1 file changed, 22 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/59131/1

diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 4b5e73b..a86605e 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -1333,7 +1333,15 @@
 {
    struct device *dev = link->dev;
    struct bus *parent = dev->bus;
-	u32 reg, buses = 0;
+	union {
+		u32 raw;
+		struct {
+			u8 primary;
+			u8 secondary;
+			u8 subordinate;
+			u8 _latency;
+		} __packed;
+	} reg, buses = { .raw = 0 };

if (state == PCI_ROUTE_SCAN) {
    	link->secondary = parent->subordinate + 1;
@@ -1341,15 +1349,16 @@
    }

if (state == PCI_ROUTE_CLOSE) {
-		buses |= 0xfeff << 8;
+		buses.primary = 0xff;
+		buses.secondary = 0xfe;
    } else if (state == PCI_ROUTE_SCAN) {
-		buses |= parent->secondary & 0xff;
-		buses |= ((u32) link->secondary & 0xff) << 8;
-		buses |= 0xff << 16; /* MAX PCI_BUS number here */
+		buses.primary = parent->secondary;
+		buses.secondary = parent->secondary;
+		buses.subordinate = 0xff; /* MAX PCI_BUS number here */
    } else if (state == PCI_ROUTE_FINAL) {
-		buses |= parent->secondary & 0xff;
-		buses |= ((u32) link->secondary & 0xff) << 8;
-		buses |= ((u32) link->subordinate & 0xff) << 16;
+		buses.primary = parent->secondary;
+		buses.secondary = parent->secondary;
+		buses.subordinate = link->subordinate;
    }

if (state == PCI_ROUTE_SCAN) {
@@ -1364,11 +1373,11 @@
     * transactions will not be propagated by the bridge if it is not
     * correctly configured.
     */
-
-	reg = pci_read_config32(dev, PCI_PRIMARY_BUS);
-	reg &= 0xff000000;
-	reg |= buses;
-	pci_write_config32(dev, PCI_PRIMARY_BUS, reg);
+	reg.raw = pci_read_config32(dev, PCI_PRIMARY_BUS);
+	reg.primary = buses.primary;
+	reg.secondary = buses.secondary;
+	reg.subordinate = buses.subordinate;
+	pci_write_config32(dev, PCI_PRIMARY_BUS, reg.raw);

if (state == PCI_ROUTE_FINAL) {
    	pci_write_config16(dev, PCI_COMMAND, link->bridge_cmd);