Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier.
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80083?usp=email )
Change subject: soc/amd: factor out non-CAR romstage to common code ......................................................................
soc/amd: factor out non-CAR romstage to common code
Since the romstage code is very similar between all AMD non-CAR SoCs, factor out a common romstage implementation. All SoCs that select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE call fill_chipset_state, so this Kconfig option can be used to determine whether to make that call. In the FSP case, fsp_m_call gets called, while in the case of an implementation that doesn't rely on an FSP to do the initialization, cbmem_initialize_empty gets called to set up CBMEM which otherwise would be done inside the FSP driver code. Since only some SoCs call fch_disable_legacy_dma_io again in romstage right after fsp_m_call, introduce the new SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP Kconfig option, so that the SoCs can specify if this call is needed or not.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I4a0695714ba08b13a58b12a490da50cb7f5a1ca9 --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc D src/soc/amd/cezanne/romstage.c M src/soc/amd/common/block/acpimmio/Kconfig M src/soc/amd/common/block/cpu/noncar/Makefile.inc A src/soc/amd/common/block/cpu/noncar/romstage.c M src/soc/amd/genoa_poc/Makefile.inc D src/soc/amd/genoa_poc/romstage.c M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/Makefile.inc D src/soc/amd/glinda/romstage.c M src/soc/amd/mendocino/Kconfig M src/soc/amd/mendocino/Makefile.inc D src/soc/amd/mendocino/romstage.c M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/Makefile.inc D src/soc/amd/phoenix/romstage.c M src/soc/amd/picasso/Makefile.inc D src/soc/amd/picasso/romstage.c 19 files changed, 50 insertions(+), 165 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/80083/1
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 42a7bf3..0ef658c 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -77,6 +77,7 @@ select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ select SOC_AMD_COMMON_FSP_PRELOAD_FSPS select SOC_AMD_COMMON_BLOCK_XHCI + select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP select SSE2 select UDK_2017_BINDING select USE_DDR4 diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 044d33e..dedf98c 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -17,7 +17,6 @@ bootblock-y += espi_util.c
romstage-y += fsp_m_params.c -romstage-y += romstage.c
ramstage-y += acpi.c ramstage-y += agesa_acpi.c diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c deleted file mode 100644 index 4fa4d84..0000000 --- a/src/soc/amd/cezanne/romstage.c +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/acpimmio.h> -#include <amdblocks/memmap.h> -#include <amdblocks/pmlib.h> -#include <amdblocks/post_codes.h> -#include <amdblocks/romstage.h> -#include <console/console.h> -#include <cpu/cpu.h> -#include <program_loading.h> -#include <romstage_common.h> - -void __noreturn romstage_main(void) -{ - post_code(POSTCODE_ROMSTAGE_MAIN); - - /* Snapshot chipset state prior to any FSP call */ - fill_chipset_state(); - - fsp_m_call(); - - /* Fixup settings FSP-M should not be changing */ - fch_disable_legacy_dma_io(); - - memmap_stash_early_dram_usage(); - - run_ramstage(); -} diff --git a/src/soc/amd/common/block/acpimmio/Kconfig b/src/soc/amd/common/block/acpimmio/Kconfig index 9881385..1ae6d4f 100644 --- a/src/soc/amd/common/block/acpimmio/Kconfig +++ b/src/soc/amd/common/block/acpimmio/Kconfig @@ -18,4 +18,10 @@ Add functions to access the PM register block via the indirect IO register access interface.
+config SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP + bool + help + Disable the legacy DMA decodes again after the call into the + reference code in romstage to fix up things. + endif # SOC_AMD_COMMON_BLOCK_ACPIMMIO diff --git a/src/soc/amd/common/block/cpu/noncar/Makefile.inc b/src/soc/amd/common/block/cpu/noncar/Makefile.inc index f8ca357..f3ada62 100644 --- a/src/soc/amd/common/block/cpu/noncar/Makefile.inc +++ b/src/soc/amd/common/block/cpu/noncar/Makefile.inc @@ -8,6 +8,7 @@ bootblock-y += write_resume_eip.c bootblock-$(CONFIG_TPM_MEASURED_BOOT) += bootblock_measure.c romstage-y += memmap.c +romstage-y += romstage.c ramstage-y += cpu.c romstage-y += cpu.c ramstage-y += memmap.c diff --git a/src/soc/amd/common/block/cpu/noncar/romstage.c b/src/soc/amd/common/block/cpu/noncar/romstage.c new file mode 100644 index 0000000..bfb1b95 --- /dev/null +++ b/src/soc/amd/common/block/cpu/noncar/romstage.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/acpimmio.h> +#include <amdblocks/post_codes.h> +#include <amdblocks/memmap.h> +#include <amdblocks/pmlib.h> +#include <amdblocks/romstage.h> +#include <amdblocks/stb.h> +#include <cbmem.h> +#include <program_loading.h> +#include <romstage_common.h> + +void __noreturn romstage_main(void) +{ + post_code(POSTCODE_ROMSTAGE_MAIN); + + if (CONFIG(WRITE_STB_BUFFER_TO_CONSOLE)) + write_stb_to_console(); + + if (CONFIG(SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE)) { + /* Snapshot chipset state prior to any reference code call. */ + fill_chipset_state(); + } + + if (CONFIG(PLATFORM_USES_FSP2_0)) { + fsp_m_call(); + } else { + cbmem_initialize_empty(); + } + + if (CONFIG(SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP)) { + /* Fixup settings the reference code should not be changing */ + fch_disable_legacy_dma_io(); + } + + memmap_stash_early_dram_usage(); + + run_ramstage(); +} diff --git a/src/soc/amd/genoa_poc/Makefile.inc b/src/soc/amd/genoa_poc/Makefile.inc index 7d54254..01bbe7b 100644 --- a/src/soc/amd/genoa_poc/Makefile.inc +++ b/src/soc/amd/genoa_poc/Makefile.inc @@ -11,8 +11,6 @@ bootblock-y += early_fch.c bootblock-y += aoac.c
-romstage-y += romstage.c - ramstage-y += acpi.c ramstage-y += aoac.c ramstage-y += chip.c diff --git a/src/soc/amd/genoa_poc/romstage.c b/src/soc/amd/genoa_poc/romstage.c deleted file mode 100644 index 66a2140..0000000 --- a/src/soc/amd/genoa_poc/romstage.c +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/post_codes.h> -#include <amdblocks/memmap.h> -#include <cbmem.h> -#include <program_loading.h> -#include <romstage_common.h> - -void __noreturn romstage_main(void) -{ - post_code(POSTCODE_ROMSTAGE_MAIN); - - cbmem_initialize_empty(); - memmap_stash_early_dram_usage(); - run_ramstage(); -} diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index b976048..d3194a2 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -78,6 +78,7 @@ select SOC_AMD_COMMON_FSP_DMI_TABLES # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_PRELOAD_FSPS + select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP select SSE2 select UDK_2017_BINDING select USE_DDR5 diff --git a/src/soc/amd/glinda/Makefile.inc b/src/soc/amd/glinda/Makefile.inc index 675712f..bc217d3 100644 --- a/src/soc/amd/glinda/Makefile.inc +++ b/src/soc/amd/glinda/Makefile.inc @@ -22,7 +22,6 @@ verstage-y += espi_util.c
romstage-y += fsp_m_params.c -romstage-y += romstage.c
ramstage-y += acpi.c ramstage-y += agesa_acpi.c diff --git a/src/soc/amd/glinda/romstage.c b/src/soc/amd/glinda/romstage.c deleted file mode 100644 index 4fa4d84..0000000 --- a/src/soc/amd/glinda/romstage.c +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/acpimmio.h> -#include <amdblocks/memmap.h> -#include <amdblocks/pmlib.h> -#include <amdblocks/post_codes.h> -#include <amdblocks/romstage.h> -#include <console/console.h> -#include <cpu/cpu.h> -#include <program_loading.h> -#include <romstage_common.h> - -void __noreturn romstage_main(void) -{ - post_code(POSTCODE_ROMSTAGE_MAIN); - - /* Snapshot chipset state prior to any FSP call */ - fill_chipset_state(); - - fsp_m_call(); - - /* Fixup settings FSP-M should not be changing */ - fch_disable_legacy_dma_io(); - - memmap_stash_early_dram_usage(); - - run_ramstage(); -} diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index 7192106..194b775 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -84,6 +84,7 @@ select SOC_AMD_COMMON_FSP_PCI select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ select SOC_AMD_COMMON_FSP_PRELOAD_FSPS + select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP select SSE2 select UDK_2017_BINDING select USE_DDR5 diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index 6cb098f..5b9216e 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -19,7 +19,6 @@ verstage-y += espi_util.c
romstage-y += fsp_m_params.c -romstage-y += romstage.c
ramstage-y += acpi.c ramstage-y += agesa_acpi.c diff --git a/src/soc/amd/mendocino/romstage.c b/src/soc/amd/mendocino/romstage.c deleted file mode 100644 index b6f3e2b..0000000 --- a/src/soc/amd/mendocino/romstage.c +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/acpimmio.h> -#include <amdblocks/memmap.h> -#include <amdblocks/pmlib.h> -#include <amdblocks/post_codes.h> -#include <amdblocks/romstage.h> -#include <amdblocks/stb.h> -#include <console/console.h> -#include <cpu/cpu.h> -#include <program_loading.h> -#include <romstage_common.h> - -void __noreturn romstage_main(void) -{ - post_code(POSTCODE_ROMSTAGE_MAIN); - - if (CONFIG(WRITE_STB_BUFFER_TO_CONSOLE)) - write_stb_to_console(); - - /* Snapshot chipset state prior to any FSP call */ - fill_chipset_state(); - - fsp_m_call(); - - /* Fixup settings FSP-M should not be changing */ - fch_disable_legacy_dma_io(); - - memmap_stash_early_dram_usage(); - - run_ramstage(); -} diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index 5bfb5b9..fd40231 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -72,6 +72,7 @@ select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UCODE select SOC_AMD_COMMON_BLOCK_XHCI + select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP select SSE2 select USE_DDR5 select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK diff --git a/src/soc/amd/phoenix/Makefile.inc b/src/soc/amd/phoenix/Makefile.inc index 0301cdc..82ce54d 100644 --- a/src/soc/amd/phoenix/Makefile.inc +++ b/src/soc/amd/phoenix/Makefile.inc @@ -22,7 +22,6 @@ verstage-y += espi_util.c
romstage-$(CONFIG_SOC_AMD_PHOENIX_FSP) += fsp_m_params.c -romstage-y += romstage.c romstage-y += soc_util.c
ramstage-y += acpi.c diff --git a/src/soc/amd/phoenix/romstage.c b/src/soc/amd/phoenix/romstage.c deleted file mode 100644 index 4fa4d84..0000000 --- a/src/soc/amd/phoenix/romstage.c +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/acpimmio.h> -#include <amdblocks/memmap.h> -#include <amdblocks/pmlib.h> -#include <amdblocks/post_codes.h> -#include <amdblocks/romstage.h> -#include <console/console.h> -#include <cpu/cpu.h> -#include <program_loading.h> -#include <romstage_common.h> - -void __noreturn romstage_main(void) -{ - post_code(POSTCODE_ROMSTAGE_MAIN); - - /* Snapshot chipset state prior to any FSP call */ - fill_chipset_state(); - - fsp_m_call(); - - /* Fixup settings FSP-M should not be changing */ - fch_disable_legacy_dma_io(); - - memmap_stash_early_dram_usage(); - - run_ramstage(); -} diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 7ca25d0..ba58c91 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -17,7 +17,6 @@ bootblock-y += early_fch.c
romstage-y += fsp_m_params.c -romstage-y += romstage.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += agesa_acpi.c diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c deleted file mode 100644 index 88e9d68..0000000 --- a/src/soc/amd/picasso/romstage.c +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/memmap.h> -#include <amdblocks/pmlib.h> -#include <amdblocks/post_codes.h> -#include <amdblocks/romstage.h> -#include <commonlib/helpers.h> -#include <console/console.h> -#include <cpu/cpu.h> -#include <program_loading.h> -#include <romstage_common.h> -#include <types.h> - -void __noreturn romstage_main(void) -{ - post_code(POSTCODE_ROMSTAGE_MAIN); - - /* Snapshot chipset state prior to any FSP call. */ - fill_chipset_state(); - - fsp_m_call(); - - memmap_stash_early_dram_usage(); - - run_ramstage(); -}
-
Felix Held (Code Review)