Change in coreboot[master]: soc/amd/cezanne: Add device tree support for I2C

[Raul Rangel (Code Review)]

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51958 )

Change subject: soc/amd/cezanne: Add device tree support for I2C
......................................................................

soc/amd/cezanne: Add device tree support for I2C

This allows the cr50 on zork to show up in ACPI.

BUG=b:183737011
TEST=Boot OS and see I2C devices initialized

Signed-off-by: Raul E Rangel 
Change-Id: Ifb5679b7bbefbf753217981874bb1bdaef35f6db
---
M src/soc/amd/cezanne/chip.c
1 file changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/51958/1

diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c
index 2612243..c2d7af7 100644
--- a/src/soc/amd/cezanne/chip.c
+++ b/src/soc/amd/cezanne/chip.c
@@ -10,6 +10,8 @@
 #include <types.h>
 #include "chip.h"

+/* Supplied by i2c.c */
+extern struct device_operations soc_amd_i2c_mmio_ops;
 /* Supplied by uart.c */
 extern struct device_operations cezanne_uart_mmio_ops;

@@ -42,6 +44,12 @@
 static void set_mmio_dev_ops(struct device *dev)
 {
    switch (dev->path.mmio.addr) {
+	case APU_I2C0_BASE:
+	case APU_I2C1_BASE:
+	case APU_I2C2_BASE:
+	case APU_I2C3_BASE:
+		dev->ops = &soc_amd_i2c_mmio_ops;
+		break;
    case APU_UART0_BASE:
    case APU_UART1_BASE:
    	dev->ops = &cezanne_uart_mmio_ops;