Change in coreboot[master]: soc/amd/cezanne/acpi/pci0.asl: Add LPC device

[Raul Rangel (Code Review)]

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held.
Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50922 )

Change subject: soc/amd/cezanne/acpi/pci0.asl: Add LPC device
......................................................................

soc/amd/cezanne/acpi/pci0.asl: Add LPC device

Signed-off-by: Raul E Rangel 
Change-Id: Iadb8e77fb618e14cd9a6c0214bb3f5ae2dbc829d
---
M src/soc/amd/cezanne/acpi/pci0.asl
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/50922/1

diff --git a/src/soc/amd/cezanne/acpi/pci0.asl b/src/soc/amd/cezanne/acpi/pci0.asl
index f9c732f..f9956b6 100644
--- a/src/soc/amd/cezanne/acpi/pci0.asl
+++ b/src/soc/amd/cezanne/acpi/pci0.asl
@@ -78,4 +78,7 @@
    	Return(CRES) /* note to change the Name buffer */
    } /* end of Method(_SB.PCI0._CRS) */

+	/* 0:14.3 - LPC */
+	#include <soc/amd/common/acpi/lpc.asl>
+
 } /* End PCI0 scope */