Change in coreboot[master]: soc/intel/alderlake: Add support for I2C6 and I2C7

[Varshit B Pandya (Code Review)]

Attention is currently required from: Maulik V Vaghela.
Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55996 )

Change subject: soc/intel/alderlake: Add support for I2C6 and I2C7
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Patch Set 7:

(2 comments)

This change is ready for review.

File src/soc/intel/alderlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/55996/comment/54ba8e93_abc28f3f 
PS6, Line 89: 		.slot = PCH_DEV_SLOT_SIO0,
> This is taken care in this patch: […]

Done

File src/soc/intel/alderlake/include/soc/pci_devs.h:

https://review.coreboot.org/c/coreboot/+/55996/comment/6467e48f_ff6be3cb 
PS6, Line 86: #define  PCH_DEV_I2C6		_PCH_DEV(SIO0, 0)
> Please remove duplicate entries

Done