Change in coreboot[master]: soc/intel/alderlake: Add option to make MRC log silent - coreboot-gerrit

31 Dec 2021


      Attention is currently required from:  Felix Singer, Nico Huber, Paul Menzel, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Andrey Petrov, Patrick Rudolph.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60441 )
Change subject: soc/intel/alderlake: Add option to make MRC log silent
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Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60441/comment/1ceb4446_0608c480 
PS5, Line 16: HAVE_DEBUG_RAM_SETUP
...
Ah, it's part of the follow-up commit. Please do it here, thanks.
Ack
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iea3b32feca0893a83fdf700798b0883d26ccc718
Gerrit-Change-Number: 60441
Gerrit-PatchSet: 6
Gerrit-Owner: Subrata Banik subratabanik@google.com
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