Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/29075
Change subject: soc/amd/stoneyridge: Define PM USB Enable register ......................................................................
soc/amd/stoneyridge: Define PM USB Enable register
Make #define definitions for PMxEF and replace the hardcoded values.
Note that this doesn't change the current functionality of the source. The existing code has been propogated from the sb//hudson port, which seems to attempt to enable 100% of all OHCI and EHCI controllers that may be present in the system.
Change-Id: I6018b0062730de19e3283a010144dfedc2b11423 Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com --- M src/soc/amd/stoneyridge/enable_usbdebug.c M src/soc/amd/stoneyridge/include/soc/southbridge.h 2 files changed, 4 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/29075/1
diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c index 0a0c3ec..27ac61f 100644 --- a/src/soc/amd/stoneyridge/enable_usbdebug.c +++ b/src/soc/amd/stoneyridge/enable_usbdebug.c @@ -26,8 +26,8 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) { /* Enable all of the USB controllers */ - outb(0xef, PM_INDEX); - outb(0x7f, PM_DATA); + outb(PM_USB_ENABLE, PM_INDEX); + outb(PM_USB_ALL_CONTROLLERS, PM_DATA);
return SOC_EHCI1_DEV; } diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index ce0af95..b9dc62a 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -101,6 +101,8 @@ #define PM_LPC_AB_NO_BYPASS_EN BIT(2) #define PM_LPC_A20_EN BIT(1) #define PM_LPC_ENABLE BIT(0) +#define PM_USB_ENABLE 0xef +#define PM_USB_ALL_CONTROLLERS 0x7f
/* FCH MISC Registers 0xfed80e00 */ #define GPP_CLK_CNTRL 0x00