Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44088 )
Change subject: [WIP] Dirty BYT SATA fix for SeaBIOS ......................................................................
[WIP] Dirty BYT SATA fix for SeaBIOS
Change-Id: I5cc4b9b1695653066f47de67afc79f08f0341cc5 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/asrock/q1900m/devicetree.cb M src/mainboard/asrock/q1900m/irqroute.h M src/mainboard/asrock/q1900m/romstage.c M src/soc/intel/baytrail/sata.c 4 files changed, 80 insertions(+), 116 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/44088/1
diff --git a/src/mainboard/asrock/q1900m/devicetree.cb b/src/mainboard/asrock/q1900m/devicetree.cb index afa6ed6..d64ccf7 100644 --- a/src/mainboard/asrock/q1900m/devicetree.cb +++ b/src/mainboard/asrock/q1900m/devicetree.cb @@ -29,14 +29,6 @@ register "gpu_pipea_port_select" = "2" # DP_C register "gpu_pipeb_port_select" = "3" # DP_D
- # Enable PIPEA as DP_C - #register "gpu_pipea_port_select" = "2" # DP_C - #register "gpu_pipea_power_cycle_delay" = "6" # 600ms - #register "gpu_pipea_power_on_delay" = "5000" # 500ms - #register "gpu_pipea_light_on_delay" = "70" # 7ms - #register "gpu_pipea_power_off_delay" = "500" # 50ms - #register "gpu_pipea_light_off_delay" = "2000" # 200ms - # VR PS2 control register "vnn_ps2_enable" = "1" register "vcc_ps2_enable" = "1" diff --git a/src/mainboard/asrock/q1900m/irqroute.h b/src/mainboard/asrock/q1900m/irqroute.h index bc6c071..72a29c3 100644 --- a/src/mainboard/asrock/q1900m/irqroute.h +++ b/src/mainboard/asrock/q1900m/irqroute.h @@ -8,7 +8,7 @@ PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \ - PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, C, D, E, F), \ PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \ @@ -29,19 +29,3 @@ PIRQ_PIC(F, DISABLE), \ PIRQ_PIC(G, DISABLE), \ PIRQ_PIC(H, DISABLE) - -/* CORE bank DIRQs - up to 16 supported */ -//#define TPAD_IRQ_OFFSET 0 -//#define TOUCH_IRQ_OFFSET 1 -//#define I8042_IRQ_OFFSET 2 -//#define ALS_IRQ_OFFSET 3 -/* Corresponding SCORE GPIO pins */ -//#define TPAD_IRQ_GPIO 55 -//#define TOUCH_IRQ_GPIO 72 -//#define I8042_IRQ_GPIO 101 -//#define ALS_IRQ_GPIO 70 - -/* SUS bank DIRQs - up to 16 supported */ -//#define CODEC_IRQ_OFFSET 0 -/* Corresponding SUS GPIO pins */ -//#define CODEC_IRQ_GPIO 9 diff --git a/src/mainboard/asrock/q1900m/romstage.c b/src/mainboard/asrock/q1900m/romstage.c index 0d48149..1d1bec9 100644 --- a/src/mainboard/asrock/q1900m/romstage.c +++ b/src/mainboard/asrock/q1900m/romstage.c @@ -1,18 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <stdint.h> -#include <string.h> -#include <cbfs.h> #include <console/console.h> +#include <device/pci_ops.h> #include <device/pnp_ops.h> -#include <soc/gpio.h> +#include <device/smbus_host.h> +#include <soc/gfx.h> #include <soc/mrc_wrapper.h> +#include <soc/pci_devs.h> #include <soc/romstage.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h>
#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
+static uint8_t spd[2][256]; + void mainboard_fill_mrc_params(struct mrc_params *mp) { /* Enable UART */ @@ -21,33 +24,30 @@ /* I'm a bit desperate. */ printk(BIOS_EMERG, "AAAAAAAA WE LIVEEEEEEEEEE\n");
- uint8_t spd[2][256]; - uint8_t *spd_raw; - size_t spd_fsize; - mp->mainboard.dram_type = DRAM_DDR3; mp->mainboard.dram_info_location = DRAM_INFO_SPD_MEM; - //mp->mainboard.weaker_odt_settings = 1; mp->mainboard.dram_is_slotted = 1; - mp->mainboard.spd_addrs[0] = 0xf0; - mp->mainboard.spd_addrs[1] = 0; // 0xf1;
- spd_raw = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, &spd_fsize); + /* NOTE: SPD must be read manually as mrc.bin's SMBus support is broken */ + enable_smbus(); + i2c_eeprom_read(0x50, 0, sizeof(spd[0]), spd[0]); + i2c_eeprom_read(0x52, 0, sizeof(spd[1]), spd[1]);
- if (!spd_raw) - die("SPD data not found."); - - memcpy(&spd[0], spd_raw, 256); - memcpy(&spd[1], spd_raw, 256); - -#if 0 + /* Patch memory type and voltage settings to make MRC happy */ spd[0][3] = 0x03; spd[1][3] = 0x03;
spd[0][6] = 0x02; spd[1][6] = 0x02; -#endif
- mp->mainboard.dram_data[0] = spd_raw; - mp->mainboard.dram_data[1] = spd_raw; + mp->mainboard.dram_data[0] = spd; + mp->mainboard.dram_data[1] = spd; + + const unsigned int gfx_dev = PCI_DEV(0, GFX_DEV, GFX_FUNC); + + uint32_t ggc = pci_read_config32(gfx_dev, GGC); + + ggc &= ~(GGC_GTT_SIZE_MASK | GGC_GSM_SIZE_MASK); + ggc |= GGC_GTT_SIZE_2MB | (0xf << 3); + pci_write_config32(gfx_dev, GGC, ggc); } diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c index 4dc3ea4..f1b9e52 100644 --- a/src/soc/intel/baytrail/sata.c +++ b/src/soc/intel/baytrail/sata.c @@ -30,24 +30,17 @@
printk(BIOS_DEBUG, "SATA: Initializing...\n");
- if (!config->sata_ahci) { - /* Set legacy or native decoding mode */ - if (config->ide_legacy_combined) { - reg8 = pci_read_config8(dev, 0x09); - reg8 &= ~0x5; - pci_write_config8(dev, 0x09, reg8); - } else { - reg8 = pci_read_config8(dev, 0x09); - reg8 |= 0x5; - pci_write_config8(dev, 0x09, reg8); - } + /* Enable BARs */ + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
- /* Set capabilities pointer */ - pci_write_config8(dev, 0x34, 0x70); - reg16 = pci_read_config16(dev, 0x70); - reg16 &= ~0xFF00; - pci_write_config16(dev, 0x70, reg16); - } + /* Set Interrupt Line */ + /* Interrupt Pin is set by D31IP.PIP */ + pci_write_config8(dev, PCI_INTERRUPT_LINE, 0x0a); + + /* Set reg 0x94 before starting configuration */ + reg32 = 0x183; + reg32 |= (config->sata_port_map ^ 0xf) << 24; + pci_write_config32(dev, 0x94, reg32);
/* Primary timing - decode enable */ reg16 = pci_read_config16(dev, 0x40); @@ -68,21 +61,59 @@ reg16 = pci_read_config16(dev, 0x92); reg16 &= ~0x003f; reg16 |= config->sata_port_map; + reg16 |= (1 << 15); /* Set ORM bit */ pci_write_config16(dev, 0x92, reg16);
+ /* 1.4 us delay after configuring port / enable bits */ + udelay(2); + + /* R_PCH_SATA_TM2 - Undocumented in EDS, set according to ref. code */ + reg32 = pci_read_config32(dev, 0x98); + reg32 &= (u32)~(0x1f80 | (1 << 6) | (1 << 5)); + reg32 |= (1 << 29) | (1 << 25) | (1 << 23) | (1 << 22) | + (1 << 20) | (1 << 19) | (1 << 18) | (1 << 9) | (1 << 5); + printk(BIOS_DEBUG, "%s: R_PCH_SATA_TM2 value is %#08x\n", __func__, reg32); + pci_write_config32(dev, 0x98, reg32); + + /* "Test mode registers" */ + sir_write(dev, 0x70, 0x00288301); + sir_write(dev, 0x54, 0x00000300); + sir_write(dev, 0x58, 0x50000000); + /* "OOB Detection Margin */ + sir_write(dev, 0x6c, 0x130C0603); + /* "Gasket Control" */ + sir_write(dev, 0xf4, 0); + + if (!config->sata_ahci) { + /* Set legacy or native decoding mode */ + if (config->ide_legacy_combined) { + reg8 = pci_read_config8(dev, 0x09); + reg8 &= ~0x5; + pci_write_config8(dev, 0x09, reg8); + } else { + reg8 = pci_read_config8(dev, 0x09); + reg8 |= 0x5; + pci_write_config8(dev, 0x09, reg8); + } + + /* Set capabilities pointer */ + pci_write_config8(dev, 0x34, 0x70); + reg16 = pci_read_config16(dev, 0x70); + reg16 &= ~0xFF00; + pci_write_config16(dev, 0x70, reg16); + } + if (config->sata_ahci) { - u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
/* Enable CR memory space decoding */ - reg16 = pci_read_config16(dev, 0x04); - reg16 |= 0x2; - pci_write_config16(dev, 0x04, reg16); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
/* Set capability register */ reg32 = read32(abar + 0x00); reg32 |= 0x0c046000; // set PSC+SSC+SALP+SSS+SAM reg32 &= ~0x00f20060; // clear SXS+EMS+PMS+gen bits - reg32 |= (0x3 << 20); // Gen3 SATA + reg32 |= (2 << 20); // Gen3 SATA write32(abar + 0x00, reg32);
/* Ports enabled */ @@ -95,19 +126,19 @@ read32(abar + 0x0c);
/* Set cap2 - Support devslp */ - reg32 = (1 << 5) | (1 << 4) | (1 << 3); - write32(abar + 0x24, reg32); + //reg32 = (1 << 5) | (1 << 4) | (1 << 3); + //write32(abar + 0x24, reg32);
/* Set PxCMD registers */ reg32 = read32(abar + 0x118); reg32 &= ~((1 << 27) | (1 << 26) | (1 << 22) | (1 << 21) | - (1 << 19) | (1 << 18) | (1 << 1)); + (1 << 19) | (1 << 18) | (1 << 1)); reg32 |= 2; write32(abar + 0x118, reg32);
reg32 = read32(abar + 0x198); reg32 &= ~((1 << 27) | (1 << 26) | (1 << 22) | (1 << 21) | - (1 << 19) | (1 << 18) | (1 << 1)); + (1 << 19) | (1 << 18) | (1 << 1)); reg32 |= 2; write32(abar + 0x198, reg32);
@@ -123,19 +154,9 @@ /* TODO(shawnn): Configure IDE SATA speed regs */ }
- /* 1.4 us delay after configuring port / enable bits */ - udelay(2); - - /* Enable clock for ports */ - reg32 = pci_read_config32(dev, 0x94); - reg32 |= 0x3f << 24; - pci_write_config32(dev, 0x94, reg32); - reg32 &= (config->sata_port_map ^ 0x3) << 24; - pci_write_config32(dev, 0x94, reg32); - /* Lock SataGc register */ reg32 = (0x1 << 31) | (0x7 << 12); - pci_write_config32(dev, 0x98, reg32); + pci_write_config32(dev, 0x9c, reg32); }
static void sata_enable(struct device *dev) @@ -143,7 +164,6 @@ config_t *config = config_of(dev); u8 reg8; u16 reg16; - u32 reg32;
southcluster_enable_dev(dev);
@@ -155,38 +175,6 @@ reg16 |= 0x60; pci_write_config16(dev, 0x90, reg16);
- /* Set reg 0x94 before starting configuration */ - reg32 = pci_read_config32(dev, 0x94); - reg32 &= (u32)(~0x1ff); - reg32 |= 0x183; - pci_write_config32(dev, 0x94, reg32); - - /* Set ORM bit */ - reg16 = pci_read_config16(dev, 0x92); - reg16 |= (1 << 15); - pci_write_config16(dev, 0x92, reg16); - - /* R_PCH_SATA_TM2 - Undocumented in EDS, set according to ref. code */ - reg32 = pci_read_config32(dev, 0x98); - reg32 &= (u32)~(0x1f80 | (1 << 6) | (1 << 5)); - reg32 |= (1 << 29) | (1 << 25) | (1 << 23) | (1 << 22) | - (1 << 20) | (1 << 19) | (1 << 18) | (1 << 9) | (1 << 5); - pci_write_config32(dev, 0x98, reg32); - - /* CMD reg - set bus master enable (BME) */ - reg8 = pci_read_config8(dev, 0x04); - reg8 |= (1 << 2); - pci_write_config8(dev, 0x04, reg8); - - /* "Test mode registers" */ - sir_write(dev, 0x70, 0x00288301); - sir_write(dev, 0x54, 0x00000300); - sir_write(dev, 0x58, 0x50000000); - /* "OOB Detection Margin */ - sir_write(dev, 0x6c, 0x130C0603); - /* "Gasket Control" */ - sir_write(dev, 0xf4, 0); - /* PCS - Enable requested SATA ports */ reg8 = pci_read_config8(dev, 0x92); reg8 &= ~0x03;
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44088 )
Change subject: soc/intel/baytrail/sata.c: Fix SATA init sequence ......................................................................
Set Ready For Review
Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44088 )
Change subject: soc/intel/baytrail/sata.c: Fix SATA init sequence ......................................................................
Patch Set 2: Code-Review+1
SeaBIOS boots from SATA on GBYT4.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44088 )
Change subject: soc/intel/baytrail/sata.c: Fix SATA init sequence ......................................................................
Patch Set 3: Code-Review+2
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44088 )
Change subject: soc/intel/baytrail/sata.c: Fix SATA init sequence ......................................................................
Patch Set 3:
Also fixes SATA on minnowboard turbot.
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44088 )
Change subject: soc/intel/baytrail/sata.c: Fix SATA init sequence ......................................................................
soc/intel/baytrail/sata.c: Fix SATA init sequence
SeaBIOS on Bay Trail would time out when trying to access a SATA drive. Turns out that there's two mistakes in the SATA initialization sequence:
- PCI register 0x94 is wrongly cleared with a bitwise-and operation. - PCI register 0x9c is instead written to 0x98, clobbering the latter.
After correcting them, SeaBIOS can boot from SATA on Asrock Q1900M.
Change-Id: I5cc4b9b1695653066f47de67afc79f08f0341cc5 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/44088 Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Máté Kukri kukri.mate@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/baytrail/sata.c 1 file changed, 2 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Máté Kukri: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c index 4dc3ea4..24c805a 100644 --- a/src/soc/intel/baytrail/sata.c +++ b/src/soc/intel/baytrail/sata.c @@ -128,14 +128,12 @@
/* Enable clock for ports */ reg32 = pci_read_config32(dev, 0x94); - reg32 |= 0x3f << 24; - pci_write_config32(dev, 0x94, reg32); - reg32 &= (config->sata_port_map ^ 0x3) << 24; + reg32 &= ~(config->sata_port_map << 24); pci_write_config32(dev, 0x94, reg32);
/* Lock SataGc register */ reg32 = (0x1 << 31) | (0x7 << 12); - pci_write_config32(dev, 0x98, reg32); + pci_write_config32(dev, 0x9c, reg32); }
static void sata_enable(struct device *dev)
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
Máté Kukri (Code Review)