Marty E. Plummer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35010 )
Change subject: coreboot.rom: add ffs headers ......................................................................
coreboot.rom: add ffs headers
Change-Id: I95b4169d1f89a403d3ec4f293479c81c3d34f602 Signed-off-by: Marty E. Plummer hanetzer@startmail.com --- M Makefile.inc 1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/35010/1
diff --git a/Makefile.inc b/Makefile.inc index 722e180..f2b3734 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1177,6 +1177,14 @@ endif
endif +ifeq ($(CONFIG_FFS_HEADER),y) + $(FPART) -C -t $@.tmp -s $(CONFIG_ROM_SIZE) -b 4k -p 0 + $(FPART) -C -t $@.tmp -s $(CONFIG_ROM_SIZE) -b 4k -p $(FMAP_FFS_HDR_2_BASE) + $(FPART) -A -t $@.tmp --size 128kb --offset $(FMAP_FFS_HDR_SIZE) --flags 0 --name HBB -p 0,$(FMAP_FFS_HDR_2_BASE) + $(FPART) -A -t $@.tmp --size $(FMAP_CBFS_SIZE) --offset $(FMAP_CBFS_BASE) --flags 0 --name COREBOOT -p 0,$(FMAP_FFS_HDR_2_BASE) + $(FPART) -A -t $@.tmp --size $(FMAP_FFS_HDR_SIZE) --offset $(FMAP_FFS_HDR_2_BASE) --flags 1 --name BACKUP_PART -p 0 + $(FPART) -A -t $@.tmp --size $(FMAP_FFS_HDR_SIZE) --offset 0 --flags 1 --name BACKUP_PART -p $(FMAP_FFS_HDR_2_BASE) +endif # ($(CONFIG_FFS_HEADER),y) mv $@.tmp $@ @printf " CBFSLAYOUT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ layout
Timothy Pearson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35010 )
Change subject: coreboot.rom: add ffs headers ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35010/4/Makefile.inc File Makefile.inc:
https://review.coreboot.org/c/coreboot/+/35010/4/Makefile.inc@1183 PS4, Line 1183: HBB Do we want to keep this consistent with the stock IBM firmware and use HBBL here?
Timothy Pearson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35010 )
Change subject: coreboot.rom: add ffs headers ......................................................................
Patch Set 4: Code-Review+1
Marty E. Plummer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35010 )
Change subject: coreboot.rom: add ffs headers ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35010/4/Makefile.inc File Makefile.inc:
https://review.coreboot.org/c/coreboot/+/35010/4/Makefile.inc@1183 PS4, Line 1183: HBB
Do we want to keep this consistent with the stock IBM firmware and use HBBL here?
Well, here I'm using a trick, primarily for indev work and the initial flash. Theoretically the current seeprom images from an open-power system is programmed to find a 'HBB' partition on the pnor and load it. Eventually that may be the right choice going forward, if we keep the FFS_HEADERs beyond the initial flash and dev testing (the idea is eventually the sbe+hbbl image on the seeprom will have been incorporated into the coreboot build (directly or as a submodule) and probably stored in the cbfs to be written to the seeproms later.
Marty E. Plummer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35010 )
Change subject: coreboot.rom: add ffs headers ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35010/4/Makefile.inc File Makefile.inc:
https://review.coreboot.org/c/coreboot/+/35010/4/Makefile.inc@1183 PS4, Line 1183: HBB
Well, here I'm using a trick, primarily for indev work and the initial flash. […]
Basically, my understanding is bootblock ~= hbbl, and ramstage and romstage are ~= hostboot and perhaps part of skiboot. Eventually, the bootblock should probably end up on the seeprom, with only ram/romstage and payloads in the cbfs, but for now we just hijack the current open-power boot path. I think there eventually should be a way to build two images for these targets: this pnor-style image for initial testing and flash, and a 'pure' coreboot.rom for use going forward (after the first flash and boot (theoretically) rewrites the seeprom with our new bootblock/hbbl).
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Marty E. Plummer (Code Review) -
Timothy Pearson (Code Review)