[M] Change in coreboot[master]: mb/amd/mayan: Update the DXIO descriptors for mayan

[Anand Vaikar (Code Review)]

Anand Vaikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74191 )

Change subject: mb/amd/mayan: Update the DXIO descriptors for mayan
......................................................................

mb/amd/mayan: Update the DXIO descriptors for mayan

Change-Id: I8b536f8a1ff4eab06f37aec0f25704525dc1b64e
Signed-off-by: Anand Vaikar 
---
M src/mainboard/amd/mayan/port_descriptors.c
1 file changed, 69 insertions(+), 20 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/74191/1

diff --git a/src/mainboard/amd/mayan/port_descriptors.c b/src/mainboard/amd/mayan/port_descriptors.c
index f52abcd..19b4cd0 100644
--- a/src/mainboard/amd/mayan/port_descriptors.c
+++ b/src/mainboard/amd/mayan/port_descriptors.c
@@ -6,48 +6,87 @@
 #include <soc/platform_descriptors.h>
 #include <types.h>

-/* TODO: Update for mayan */

-static const fsp_dxio_descriptor mayan_dxio_descriptors[] = {
+
+static fsp_dxio_descriptor mayan_dxio_descriptors[] = {
    {
+		// MXM
    	.engine_type = PCIE_ENGINE,
    	.port_present = true,
    	.start_logical_lane = 0,
-		.end_logical_lane = 0,
-		.device_number = 2,
+		.end_logical_lane = 3,
+		.device_number = 1,
    	.function_number = 1,
-		.link_speed_capability = GEN3,
+		.link_speed_capability = GEN_MAX,
    	.turn_off_unused_lanes = true,
    	.link_aspm = 2,
-		.link_hotplug = 3,
-		.clk_req = CLK_REQ3,
+		.link_aspm_L1_1 = 1,
+		.link_aspm_L1_2 = 1,
+		.link_hotplug = 0,
+		.gpio_group_id = 4,
+		.clk_pm_support = 1,
+		.clk_req = CLK_REQ0,
+		.eq_preset = 3,
+		.port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}
    },
    {
+		// M2 SSD0-NVME
    	.engine_type = PCIE_ENGINE,
    	.port_present = true,
-		.start_logical_lane = 1,
-		.end_logical_lane = 1,
+		.start_logical_lane = 16,
+		.end_logical_lane = 19,
+		.device_number = 2,
+		.function_number = 4,
+		.link_speed_capability = GEN_MAX,
+		.turn_off_unused_lanes = true,
+		.link_aspm = 2,
+		.link_aspm_L1_1 = 1,
+		.link_aspm_L1_2 = 1,
+		.link_hotplug = 0,
+		.gpio_group_id = 27,
+		.clk_pm_support = 1,
+		.clk_req = CLK_REQ4,
+		.eq_preset = 3,
+		.port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}
+	},
+	{
+		// X1
+		.engine_type = PCIE_ENGINE,
+		.port_present = true,
+		.start_logical_lane = 15,
+		.end_logical_lane = 15,
    	.device_number = 2,
    	.function_number = 2,
-		.link_speed_capability = GEN3,
+		.link_speed_capability = GEN_MAX,
    	.turn_off_unused_lanes = true,
    	.link_aspm = 2,
-		.link_hotplug = 3,
-		.clk_req = CLK_REQ1,
+		.link_aspm_L1_1 = 1,
+		.link_aspm_L1_2 = 1,
+		.link_hotplug = 0,
+		//.gpio_group_id = 30,
+		.clk_pm_support = 1,
+		.clk_req = CLK_REQ6,
+		.eq_preset = 3,
+		.port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}
    },
    {
+		// DT
    	.engine_type = PCIE_ENGINE,
    	.port_present = true,
-		.start_logical_lane = 2,
-		.end_logical_lane = 3,
-		.device_number = 2,
-		.function_number = 3,
-		.link_speed_capability = GEN3,
+		.start_logical_lane = 8,
+		.end_logical_lane = 9,
+		.device_number = 1,
+		.function_number = 2,
+		.link_speed_capability = GEN_MAX,
    	.turn_off_unused_lanes = true,
    	.link_aspm = 2,
-		.link_hotplug = 3,
-		.gpio_group_id = GPIO_27,
-		.clk_req = CLK_REQ0,
+		.link_aspm_L1_1 = 1,
+		.link_aspm_L1_2 = 1,
+		.link_hotplug = 0,
+		.clk_pm_support = 0,
+		.clk_req = CLK_REQ1,
+		.eq_preset = 3,
+		.port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}
    },
 };