Change in coreboot[master]: nb/x4x/raminit: Rewrite SPD decode and timing selection

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change.  Please visit

https://review.coreboot.org/19143

to look at the new patch set (#15).

Change subject: nb/x4x/raminit: Rewrite SPD decode and timing selection
......................................................................

nb/x4x/raminit: Rewrite SPD decode and timing selection

This is mostly written from scratch and uses common spd ddr2 decode
functions.

This improves the following:
* This fixes incorrect CAS/Freq detection on DDR2;

* Timings selection does not use loops;

* Removes ddr3 spd decode, since there is no DDR3 raminit. For this it
  would be nice to use similar common functions for DDR3;

* Raminit would bail out if dimm was unsupported, now in some cases it
  just marks the dimm slot as empty;

* It dramatically reduces stack usage since it does not allocate 4
  times 256 bytes to store full SPDs, amongs other unused things that
  were stored in sysinfo.

* Reports when no dimms are present.

* Uses i2c block read to read SPD which is about 5 times faster than
  bytewise read, with a fallback to smbus mode in case of failure.

TESTED: on ga-g41m-es2l.

Change-Id: I760eeaa3bd4f2bc25a517ddb1b9533c971454071
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/x4x/raminit.c
M src/northbridge/intel/x4x/raminit_ddr2.c
M src/northbridge/intel/x4x/x4x.h
3 files changed, 294 insertions(+), 380 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/19143/15