Change in coreboot[master]: arch/x86: Always display MTRRs when running the next stage

[Arthur Heymans (Code Review)]

Attention is currently required from: Arthur Heymans.
Hello Arthur Heymans,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/55507

to review the following change.

Change subject: arch/x86: Always display MTRRs when running the next stage
......................................................................

arch/x86: Always display MTRRs when running the next stage

This change does the following:
- expose DISPLAY_MTRR to all ARCH_86: coreboot does not support very
  old X86 CPUs lacking MTRRs
- call display_mtrr() when running a program: it's useful to know in
  what caching environment the next stage will run.

Change-Id: I0d878928c0899b7a2bc66d2600bf0e40494c74df
Signed-off-by: Arthur Heymans 
---
M src/arch/x86/boot.c
M src/arch/x86/postcar.c
M src/cpu/x86/Kconfig.debug_cpu
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/common/Kconfig.common
M src/soc/intel/quark/bootblock/bootblock.c
6 files changed, 4 insertions(+), 10 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/55507/1

diff --git a/src/arch/x86/boot.c b/src/arch/x86/boot.c
index 777a0b7..bade982 100644
--- a/src/arch/x86/boot.c
+++ b/src/arch/x86/boot.c
@@ -2,6 +2,7 @@

#include <arch/boot/boot.h>
 #include <commonlib/helpers.h>
+#include <cpu/x86/mtrr.h>
 #include <console/console.h>
 #include <program_loading.h>
 #include <ip_checksum.h>
@@ -21,6 +22,8 @@

void arch_prog_run(struct prog *prog)
 {
+	display_mtrrs();
+
 #if ENV_RAMSTAGE && defined(__x86_64__)
    const uint32_t arg = pointer_to_uint32_safe(prog_entry_arg(prog));
    const uint32_t entry = pointer_to_uint32_safe(prog_entry(prog));
diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c
index 1df8c44..b185279 100644
--- a/src/arch/x86/postcar.c
+++ b/src/arch/x86/postcar.c
@@ -32,8 +32,6 @@

timestamp_add_now(TS_START_POSTCAR);

-	display_mtrrs();
-
    /* Load and run ramstage. */
    run_ramstage();
 }
diff --git a/src/cpu/x86/Kconfig.debug_cpu b/src/cpu/x86/Kconfig.debug_cpu
index 0569341..d721bc2 100644
--- a/src/cpu/x86/Kconfig.debug_cpu
+++ b/src/cpu/x86/Kconfig.debug_cpu
@@ -5,12 +5,9 @@
    bool "Output verbose Cache-as-RAM debug messages"
    depends on HAVE_DEBUG_CAR

-config HAVE_DISPLAY_MTRRS
-	bool
-
 config DISPLAY_MTRRS
    bool "Display intermediate MTRR settings"
-	depends on HAVE_DISPLAY_MTRRS
+	depends on ARCH_X86

config DEBUG_SMM_RELOCATION
    bool "Debug SMM relocation code"
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 5cdfb54..e5b32d9 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -19,7 +19,6 @@
    select CACHE_MRC_SETTINGS
    select CPU_INTEL_HASWELL
    select MRC_SETTINGS_PROTECT
-	select HAVE_DISPLAY_MTRRS
    select HAVE_SMI_HANDLER
    select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
    select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
diff --git a/src/soc/intel/common/Kconfig.common b/src/soc/intel/common/Kconfig.common
index f39571e..5f1f608 100644
--- a/src/soc/intel/common/Kconfig.common
+++ b/src/soc/intel/common/Kconfig.common
@@ -1,7 +1,6 @@
 config SOC_INTEL_COMMON
    bool
    select AZALIA_PLUGIN_SUPPORT
-	select HAVE_DISPLAY_MTRRS
    select ACPI_SOC_NVS
    help
      common code for Intel SOCs
diff --git a/src/soc/intel/quark/bootblock/bootblock.c b/src/soc/intel/quark/bootblock/bootblock.c
index 2e1a099..426a6a4 100644
--- a/src/soc/intel/quark/bootblock/bootblock.c
+++ b/src/soc/intel/quark/bootblock/bootblock.c
@@ -97,8 +97,6 @@
 {
    if (CONFIG(ENABLE_DEBUG_LED_SOC_INIT_ENTRY))
    	light_sd_led();
-
-	display_mtrrs();
 }

void platform_prog_run(struct prog *prog)