Change in coreboot[master]: mb/intel/cedarisland/gpio: use macros for bidirectional pads
Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43456 )
Change subject: mb/intel/cedarisland/gpio: use macros for bidirectional pads ......................................................................
mb/intel/cedarisland/gpio: use macros for bidirectional pads
The configuration contains pads in which both buffers (Tx/Rx) [1] are enabled. Therefore, they are bidirectional. Use the new macros instead PAD_CFG_GPIO_BIDIRECT() [2] of common _PAD_CFG_STRUCT() to configure these pads.
[1] Intel document #549921 [2] https://review.coreboot.org/c/coreboot/+/42914
Change-Id: I32a10ead1d965811f6e644124ba84ceb2264ddc4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/intel/cedarisland_crb/include/gpio.h 1 file changed, 10 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/43456/1
diff --git a/src/mainboard/intel/cedarisland_crb/include/gpio.h b/src/mainboard/intel/cedarisland_crb/include/gpio.h index cd15fed..2a5fb11 100644 --- a/src/mainboard/intel/cedarisland_crb/include/gpio.h +++ b/src/mainboard/intel/cedarisland_crb/include/gpio.h @@ -173,10 +173,7 @@ /* GPP_C9 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, RSMRST, OFF, DRIVER), /* GPP_C10 - GPIO */ - _PAD_CFG_STRUCT(GPP_C10, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_C10, 0, NONE, RSMRST, OFF, ACPI), /* GPP_C11 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_C11, NONE, RSMRST, OFF, ACPI), /* GPP_C12 - GPIO */ @@ -318,10 +315,7 @@ /* GPP_I3 - LAN_TDI */ PAD_CFG_NF(GPP_I3, NONE, RSMRST, NF2), /* GPP_I4 - GPIO */ - _PAD_CFG_STRUCT(GPP_I4, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_I4, 0, NONE, RSMRST, OFF, ACPI), /* GPP_I5 - GPIO */ PAD_CFG_GPO(GPP_I5, 0, RSMRST), /* GPP_I6 - GPIO */ @@ -364,17 +358,11 @@ /* GPP_J12 - GPIO */ PAD_CFG_GPO(GPP_J12, 0, RSMRST), /* GPP_J13 - GPIO */ - _PAD_CFG_STRUCT(GPP_J13, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_J13, 0, NONE, RSMRST, OFF, ACPI), /* GPP_J14 - GPIO */ PAD_CFG_GPO(GPP_J14, 0, RSMRST), /* GPP_J15 - GPIO */ - _PAD_CFG_STRUCT(GPP_J15, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_J15, 0, NONE, RSMRST, OFF, ACPI), /* GPP_J16 - GPIO */ PAD_CFG_GPO(GPP_J16, 0, RSMRST), /* GPP_J17 - GPIO */ @@ -468,42 +456,24 @@
/* ------- GPIO Group GPP_H ------- */ /* GPP_H0 - GPIO */ - _PAD_CFG_STRUCT(GPP_H0, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_H0, 0, NONE, RSMRST, OFF, ACPI), /* GPP_H1 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, RSMRST, OFF, ACPI), /* GPP_H2 - GPIO */ - _PAD_CFG_STRUCT(GPP_H2, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_H2, 0, NONE, RSMRST, OFF, ACPI), /* GPP_H3 - GPIO */ - _PAD_CFG_STRUCT(GPP_H3, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_H3, 0, NONE, RSMRST, OFF, ACPI), /* GPP_H4 - GPIO */ - _PAD_CFG_STRUCT(GPP_H4, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_H4, 0, NONE, RSMRST, OFF, ACPI), /* GPP_H5 - RESERVED */ /* GPP_H6 - SRCCLKREQ12# */ PAD_CFG_NF(GPP_H6, NONE, RSMRST, NF1), /* GPP_H7 - GPIO */ - _PAD_CFG_STRUCT(GPP_H7, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_H7, 0, NONE, RSMRST, OFF, ACPI), /* GPP_H8 - SRCCLKREQ14# */ PAD_CFG_NF(GPP_H8, NONE, RSMRST, NF1), /* GPP_H9 - GPIO */ - _PAD_CFG_STRUCT(GPP_H9, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_H9, 0, NONE, RSMRST, OFF, ACPI), /* GPP_H10 - RESERVED */ /* GPP_H11 - RESERVED */ /* GPP_H12 - GPIO */
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43456
to look at the new patch set (#2).
Change subject: mb/intel/cedarisland/gpio: use macros for bidirectional pads ......................................................................
mb/intel/cedarisland/gpio: use macros for bidirectional pads
The configuration contains pads in which both buffers (Tx/Rx) [1] are enabled. Therefore, they are bidirectional. Use the new macros instead PAD_CFG_GPIO_BIDIRECT() [2] of common _PAD_CFG_STRUCT() to configure these pads.
[1] Intel document #336067-007US [2] https://review.coreboot.org/c/coreboot/+/42914
Change-Id: I32a10ead1d965811f6e644124ba84ceb2264ddc4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/intel/cedarisland_crb/include/gpio.h 1 file changed, 10 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/43456/2
Hello Lance Zhao, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43456
to look at the new patch set (#3).
Change subject: mb/intel/cedarisland/gpio: use macros for bidirectional pads ......................................................................
mb/intel/cedarisland/gpio: use macros for bidirectional pads
The configuration contains pads in which both buffers (Tx/Rx) [1] are enabled. Use the new PAD_CFG_GPIO_BIDIRECT() macro [2] instead of common _PAD_CFG_STRUCT() to configure these pads.
[1] Intel document #336067-007US [2] https://review.coreboot.org/c/coreboot/+/42914
Change-Id: I32a10ead1d965811f6e644124ba84ceb2264ddc4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/intel/cedarisland_crb/include/gpio.h 1 file changed, 10 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/43456/3
Maxim Polyakov has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43456 )
Change subject: mb/intel/cedarisland/gpio: use macros for bidirectional pads ......................................................................
Abandoned
-
Maxim Polyakov (Code Review)