[XS] Change in coreboot[main]: soc/intel/xeon_sp: Remove assert when creating DMAR component

[Shuo Liu (Code Review)]

Attention is currently required from: Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Tim Chu.

Shuo Liu has posted comments on this change by Jincheng Li. ( https://review.coreboot.org/c/coreboot/+/85737?usp=email )

Change subject: soc/intel/xeon_sp: Remove assert when creating DMAR component
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Patch Set 1:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/85737/comment/6e034568_034557d1?usp... :
PS1, Line 10: Remove
> You are writing that multiple domains *share* a VTD, how does that work when you iterate only over d […]

Good question. Got a quick check but agree that more checks are needed before moving ahead.

1 - For DRHD, The DRHD adding code is per VTD
https://github.com/coreboot/coreboot/blob/main/src/soc/intel/xeon_sp/uncore_...,

While when it comes to cover the end points, it iterates the whole stack,
https://github.com/coreboot/coreboot/blob/main/src/soc/intel/xeon_sp/uncore_.... So IOAT domains without VTD are covered as well. (maybe some comments needed to be added here to be more clear).

2 - For RHSA, it is added per VTD, so no impact

https://github.com/coreboot/coreboot/blob/main/src/soc/intel/xeon_sp/uncore_...

3 - For SATC, it is added per domain, so no impact

https://github.com/coreboot/coreboot/blob/main/src/soc/intel/xeon_sp/uncore_...

4 - For ATSR, it is added per VTD but covers only PCIe root ports, so not impacting IOAT end points. (But here need to confirm for ATSR no need to add end-points)

https://github.com/coreboot/coreboot/blob/main/src/soc/intel/xeon_sp/uncore_...