Change in coreboot[master]: mb/intel/adlrvp: Enable UFS and ISH for ADL-N RVP

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Daniil Lunev, Subrata Banik, Wonkyu Kim, Paul Menzel, Rizwan Qureshi, Angel Pons, Meera Ravindranath, Patrick Rudolph, Gwendal Grignou.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62662 )

Change subject: mb/intel/adlrvp: Enable UFS and ISH for ADL-N RVP
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Patch Set 6: Code-Review+2

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/62662/comment/0ecea88c_f4db7f3b 
PS6, Line 9: the parent
> Actually, `function 0`

suggestion:
```
In order to enable the UFS controller (PCI device 12.7), the PCI specification
says that the device at function 0 in the same slot must also be enabled, 
(which is the ISH). Therefore, this CL enables both the UFS controller and ISH.
```

File src/mainboard/intel/adlrvp/devicetree_n.cb:

https://review.coreboot.org/c/coreboot/+/62662/comment/ee9a4c80_3de82882 
PS3, Line 283: on
> FSP should have migrate this PCI device config space under func 0 using swaping isn't it?

IIUC, the FSP (and the Intel SoCs themselves AFAIK) only support remapping of the PCIe RPs, therefore I believe it is up to the mainboard designer to ensure that their device is PCI compliant w/r/t function 0 being enabled when other functions are also enabled. Right now, the coreboot PCI scanning code will skip scanning functions 1-7 if function 0 is not enabled, unless the multi-function bit is set in the header type (https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/src...)