Change in coreboot[master]: mb/siemens/chili: Drop ineffective `SaGv` setting

[Angel Pons (Code Review)]

Attention is currently required from:  Felix Singer, Nico Huber.
Hello  Felix Singer, Nico Huber,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/56205

to review the following change.

Change subject: mb/siemens/chili: Drop ineffective `SaGv` setting
......................................................................

mb/siemens/chili: Drop ineffective `SaGv` setting

SaGv is only available on ULT/ULX processors, which use PCH-LP. Given
that the Siemens Chili board selects `SOC_INTEL_CANNONLAKE_PCH_H`, it
does not use ULT/ULX processors, and thus does not support SaGv. Drop
the `SaGv` setting from the devicetrees, as it has no effect.

Change-Id: I5be518cce08206ad149efd1665e44a7111b24202
Signed-off-by: Angel Pons 
---
M src/mainboard/siemens/chili/variants/base/devicetree.cb
M src/mainboard/siemens/chili/variants/chili/devicetree.cb
2 files changed, 0 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/56205/1

diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb
index ccbe804..81dae2e 100644
--- a/src/mainboard/siemens/chili/variants/base/devicetree.cb
+++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb
@@ -2,7 +2,6 @@

chip soc/intel/cannonlake
    # FSP configuration
-	register "SaGv" = "SaGv_Enabled"
    register "RMT" = "0"

register "PchHdaDspEnable" = "0"
diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb
index 4416dbf..b4d9970 100644
--- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb
+++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb
@@ -2,7 +2,6 @@

chip soc/intel/cannonlake
    # FSP configuration
-	register "SaGv" = "SaGv_Enabled"
    register "RMT" = "0"

register "PchHdaDspEnable" = "0"