Change in coreboot[master]: mainboard/google/hatch: Move gpio GPP_H3 config up from baseboard
Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37922 )
Change subject: mainboard/google/hatch: Move gpio GPP_H3 config up from baseboard ......................................................................
mainboard/google/hatch: Move gpio GPP_H3 config up from baseboard
The baseboard GPIO table definitions are too straineous to the extend that variants need to redefine assumptions back to NC. Invert this so that baseboard by default assumes the safer NC and move the specific board configurations to their respective places.
This patch handles the GPP_H3 gpio config for easier review. This toggles the MAX amp which not all boards have. Move the pin configuration to boards with the respective devicetree configuration following on from the theme of commit b417786525.
BUG=b:142094759 BRANCH=none TEST=builds
Change-Id: Iefd2223af79a13c8a42d07bc10b2772dbff6d3e5 Signed-off-by: Edward O'Callaghan quasisec@google.com --- M src/mainboard/google/hatch/variants/akemi/gpio.c M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/dratini/gpio.c M src/mainboard/google/hatch/variants/jinlon/gpio.c M src/mainboard/google/hatch/variants/kindred/gpio.c M src/mainboard/google/hatch/variants/kohaku/gpio.c M src/mainboard/google/hatch/variants/mushu/gpio.c M src/mainboard/google/hatch/variants/stryke/gpio.c 8 files changed, 20 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/37922/1
diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c index 1000a08..ff4f358 100644 --- a/src/mainboard/google/hatch/variants/akemi/gpio.c +++ b/src/mainboard/google/hatch/variants/akemi/gpio.c @@ -134,6 +134,8 @@ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* F22 : EMMC_RESET# ==> EMMC_RST_L */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H6 : NC */ PAD_NC(GPP_H6, NONE), /* H7 : NC */ diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 2c3bf8d..dcd987f 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -334,8 +334,8 @@ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* H2 : CNV_CLKREQ0 */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), - /* H3 : SPKR_PA_EN */ - PAD_CFG_GPO(GPP_H3, 0, DEEP), + /* H3 : GPP_H3 ==> NC */ + PAD_NC(GPP_H3, NONE), /* H4 : PCH_I2C_PEN_SDA */ PAD_NC(GPP_H4, NONE), /* H5 : PCH_I2C_PEN_SCL */ diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c index aa32e6e..3a2ceaf 100644 --- a/src/mainboard/google/hatch/variants/dratini/gpio.c +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -59,6 +59,8 @@ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* F22 : EMMC_RESET# ==> EMMC_RST_L */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 03ea2e2..1e945cc 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -55,6 +55,8 @@ PAD_NC(GPP_F21, NONE), /* F22 : EMMC_RESET# ==> NC */ PAD_NC(GPP_F22, NONE), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ diff --git a/src/mainboard/google/hatch/variants/kindred/gpio.c b/src/mainboard/google/hatch/variants/kindred/gpio.c index 7b62027..fdad243 100644 --- a/src/mainboard/google/hatch/variants/kindred/gpio.c +++ b/src/mainboard/google/hatch/variants/kindred/gpio.c @@ -61,6 +61,8 @@ PAD_NC(GPP_F21, NONE), /* F22 : EMMC_RESET# ==> NC */ PAD_NC(GPP_F22, NONE), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ @@ -116,6 +118,8 @@ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* F22 : EMMC_RESET# ==> EMMC_RST_L */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ @@ -165,6 +169,8 @@ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* F22 : EMMC_RESET# ==> EMMC_RST_L */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 50d0cb3..5f9ca2d 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -77,6 +77,8 @@ PAD_NC(GPP_G5, NONE), /* G6 : GPP_G6 ==> NC */ PAD_NC(GPP_G6, NONE), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H4 : PCH_I2C_PEN_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* H5 : PCH_I2C_PEN_SCL */ diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c index 05278fb..ce589e5 100644 --- a/src/mainboard/google/hatch/variants/mushu/gpio.c +++ b/src/mainboard/google/hatch/variants/mushu/gpio.c @@ -35,6 +35,8 @@ PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT)}; /* C15 : WWAN_DPR_SAR_ODL */ PAD_CFG_GPO(GPP_C15, 1, DEEP), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP),
const struct pad_config *override_gpio_table(size_t *num) { diff --git a/src/mainboard/google/hatch/variants/stryke/gpio.c b/src/mainboard/google/hatch/variants/stryke/gpio.c index c548544..f3f40a7 100644 --- a/src/mainboard/google/hatch/variants/stryke/gpio.c +++ b/src/mainboard/google/hatch/variants/stryke/gpio.c @@ -49,6 +49,8 @@ PAD_NC(GPP_F21, NONE), /* F22 : NC */ PAD_NC(GPP_F22, NONE), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37922
to look at the new patch set (#3).
Change subject: mainboard/google/hatch: Move gpio GPP_H3 config up from baseboard ......................................................................
mainboard/google/hatch: Move gpio GPP_H3 config up from baseboard
The baseboard GPIO table definitions are too straineous to the extend that variants need to redefine assumptions back to NC. Invert this so that baseboard by default assumes the safer NC and move the specific board configurations to their respective places.
This patch handles the GPP_H3 gpio config for easier review. This toggles the MAX amp which not all boards have. Move the pin configuration to boards with the respective devicetree configuration following on from the theme of commit b417786525.
BUG=b:142094759 BRANCH=none TEST=builds
Change-Id: Iefd2223af79a13c8a42d07bc10b2772dbff6d3e5 Signed-off-by: Edward O'Callaghan quasisec@google.com --- M src/mainboard/google/hatch/variants/akemi/gpio.c M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/dratini/gpio.c M src/mainboard/google/hatch/variants/jinlon/gpio.c M src/mainboard/google/hatch/variants/kindred/gpio.c M src/mainboard/google/hatch/variants/kohaku/gpio.c M src/mainboard/google/hatch/variants/mushu/gpio.c M src/mainboard/google/hatch/variants/stryke/gpio.c 8 files changed, 20 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/37922/3
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37922 )
Change subject: mainboard/google/hatch: Move gpio GPP_H3 config up from baseboard ......................................................................
Patch Set 3: Code-Review+2
Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37922 )
Change subject: mainboard/google/hatch: Move gpio GPP_H3 config up from baseboard ......................................................................
mainboard/google/hatch: Move gpio GPP_H3 config up from baseboard
The baseboard GPIO table definitions are too straineous to the extend that variants need to redefine assumptions back to NC. Invert this so that baseboard by default assumes the safer NC and move the specific board configurations to their respective places.
This patch handles the GPP_H3 gpio config for easier review. This toggles the MAX amp which not all boards have. Move the pin configuration to boards with the respective devicetree configuration following on from the theme of commit b417786525.
BUG=b:142094759 BRANCH=none TEST=builds
Change-Id: Iefd2223af79a13c8a42d07bc10b2772dbff6d3e5 Signed-off-by: Edward O'Callaghan quasisec@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/37922 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/hatch/variants/akemi/gpio.c M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/dratini/gpio.c M src/mainboard/google/hatch/variants/jinlon/gpio.c M src/mainboard/google/hatch/variants/kindred/gpio.c M src/mainboard/google/hatch/variants/kohaku/gpio.c M src/mainboard/google/hatch/variants/mushu/gpio.c M src/mainboard/google/hatch/variants/stryke/gpio.c 8 files changed, 20 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c index 0e3e46f..cfc185e 100644 --- a/src/mainboard/google/hatch/variants/akemi/gpio.c +++ b/src/mainboard/google/hatch/variants/akemi/gpio.c @@ -122,6 +122,8 @@ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* F22 : EMMC_RESET# ==> EMMC_RST_L */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H6 : NC */ PAD_NC(GPP_H6, NONE), /* H7 : NC */ diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 2c3bf8d..dcd987f 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -334,8 +334,8 @@ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* H2 : CNV_CLKREQ0 */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), - /* H3 : SPKR_PA_EN */ - PAD_CFG_GPO(GPP_H3, 0, DEEP), + /* H3 : GPP_H3 ==> NC */ + PAD_NC(GPP_H3, NONE), /* H4 : PCH_I2C_PEN_SDA */ PAD_NC(GPP_H4, NONE), /* H5 : PCH_I2C_PEN_SCL */ diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c index 204715b..fd59060 100644 --- a/src/mainboard/google/hatch/variants/dratini/gpio.c +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -59,6 +59,8 @@ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* F22 : EMMC_RESET# ==> EMMC_RST_L */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 7d2ecf2..12d96d8 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -59,6 +59,8 @@ PAD_NC(GPP_F21, NONE), /* F22 : EMMC_RESET# ==> NC */ PAD_NC(GPP_F22, NONE), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ diff --git a/src/mainboard/google/hatch/variants/kindred/gpio.c b/src/mainboard/google/hatch/variants/kindred/gpio.c index 19956b4..fbb47f9 100644 --- a/src/mainboard/google/hatch/variants/kindred/gpio.c +++ b/src/mainboard/google/hatch/variants/kindred/gpio.c @@ -65,6 +65,8 @@ PAD_NC(GPP_F21, NONE), /* F22 : EMMC_RESET# ==> NC */ PAD_NC(GPP_F22, NONE), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ @@ -124,6 +126,8 @@ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* F22 : EMMC_RESET# ==> EMMC_RST_L */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ @@ -177,6 +181,8 @@ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* F22 : EMMC_RESET# ==> EMMC_RST_L */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 837abb3..8fd203d 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -77,6 +77,8 @@ PAD_NC(GPP_G5, NONE), /* G6 : GPP_G6 ==> NC */ PAD_NC(GPP_G6, NONE), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H4 : PCH_I2C_PEN_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* H5 : PCH_I2C_PEN_SCL */ diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c index 862b28f..09e1594 100644 --- a/src/mainboard/google/hatch/variants/mushu/gpio.c +++ b/src/mainboard/google/hatch/variants/mushu/gpio.c @@ -39,6 +39,8 @@ * using this pin, expose this pin to driver. */ PAD_CFG_GPO(GPP_C15, 1, DEEP), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), };
const struct pad_config *override_gpio_table(size_t *num) diff --git a/src/mainboard/google/hatch/variants/stryke/gpio.c b/src/mainboard/google/hatch/variants/stryke/gpio.c index 4d0eba9..82ffb6c 100644 --- a/src/mainboard/google/hatch/variants/stryke/gpio.c +++ b/src/mainboard/google/hatch/variants/stryke/gpio.c @@ -53,6 +53,8 @@ PAD_NC(GPP_F21, NONE), /* F22 : NC */ PAD_NC(GPP_F22, NONE), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */
-
Edward O'Callaghan (Code Review) -
Furquan Shaikh (Code Review)