Change in coreboot[master]: soc/amd/common: add and use fch_enable_ioapic_decode

[Martin Roth (Code Review)]

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50513 )

Change subject: soc/amd/common: add and use fch_enable_ioapic_decode
......................................................................

soc/amd/common: add and use fch_enable_ioapic_decode

The default value of this bit is 0, so set it right before calling
setup_ioapic to make sure that it's set and not to have to rely on FSP
doing the right thing.

Change-Id: Ife886451a6927965769282fc5644c2085abb9585
Signed-off-by: Felix Held 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50513
Reviewed-by: Raul Rangel 
Reviewed-by: Marshall Dawson 
Tested-by: build bot (Jenkins) 
---
M src/soc/amd/common/block/acpimmio/mmio_util.c
M src/soc/amd/common/block/include/amdblocks/acpimmio.h
M src/soc/amd/common/block/smbus/sm.c
3 files changed, 8 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Marshall Dawson: Looks good to me, approved
  Raul Rangel: Looks good to me, approved

diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c
index 1cacd44..a19a28b 100644
--- a/src/soc/amd/common/block/acpimmio/mmio_util.c
+++ b/src/soc/amd/common/block/acpimmio/mmio_util.c
@@ -74,6 +74,11 @@
    pm_io_write32(PM_DECODE_EN, pm_io_read32(PM_DECODE_EN) | LEGACY_IO_EN);
 }

+void fch_enable_ioapic_decode(void)
+{
+	pm_write32(PM_DECODE_EN, pm_read32(PM_DECODE_EN) | FCH_IOAPIC_EN);
+}
+
 /* PM registers are accessed a byte at a time via CD6/CD7 */
 uint8_t pm_io_read8(uint8_t reg)
 {
diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
index 4b80a28..19decdd 100644
--- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h
+++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
@@ -17,6 +17,7 @@
 #define PM_DECODE_EN			0x00
 #define   SMBUS_ASF_IO_BASE_SHIFT	8
 #define   SMBUS_ASF_IO_BASE_MASK	(0xff << SMBUS_ASF_IO_BASE_SHIFT)
+#define   FCH_IOAPIC_EN			(1 << 5)
 #define   SMBUS_ASF_IO_EN		(1 << 4)
 #define   CF9_IO_EN			(1 << 1)
 #define   LEGACY_IO_EN			(1 << 0)
@@ -75,6 +76,7 @@
 void fch_enable_cf9_io(void);
 void fch_enable_legacy_io(void);
 void fch_io_enable_legacy_io(void);
+void fch_enable_ioapic_decode(void);

/* Access PM registers using IO cycles */
 uint8_t pm_io_read8(uint8_t reg);
diff --git a/src/soc/amd/common/block/smbus/sm.c b/src/soc/amd/common/block/smbus/sm.c
index 1ec2730..0b219e0 100644
--- a/src/soc/amd/common/block/smbus/sm.c
+++ b/src/soc/amd/common/block/smbus/sm.c
@@ -11,6 +11,7 @@

static void sm_init(struct device *dev)
 {
+	fch_enable_ioapic_decode();
    setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
 }