Change in coreboot[master]: mb/google/herobrine: Initialize USB by calling SOC method

[Shelley Chen (Code Review)]

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56093 )

Change subject: mb/google/herobrine: Initialize USB by calling SOC method
......................................................................

mb/google/herobrine: Initialize USB by calling SOC method

Initialize by calling `setup_usb_host0()` from SOC code

BUG=b:182963902
TEST=Validated USB enumeration on qcom sc7280 development board

Signed-off-by: Sandeep Maheswaram 
Change-Id: Ic378352a97e4f3ed89089f1f7545f8ebb172b1f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56093
Tested-by: build bot (Jenkins) 
Reviewed-by: Shelley Chen 
---
M src/mainboard/google/herobrine/mainboard.c
M src/mainboard/google/herobrine/romstage.c
2 files changed, 26 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Shelley Chen: Looks good to me, approved

diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c
index 82c5fa9..e64fb15 100644
--- a/src/mainboard/google/herobrine/mainboard.c
+++ b/src/mainboard/google/herobrine/mainboard.c
@@ -12,6 +12,20 @@
 #include <soc/qupv3_config_common.h>
 #include <soc/qup_se_handlers_common.h>
 #include <soc/qcom_qup_se.h>
+#include <soc/usb/usb_common.h>
+#include <soc/usb/snps_usb_phy.h>
+
+static struct usb_board_data usb0_board_data = {
+	.parameter_override_x0 = 0xe6,
+	.parameter_override_x1 = 0x8b,
+	.parameter_override_x2 = 0x16,
+	.parameter_override_x3 = 0x03,
+};
+
+static void setup_usb(void)
+{
+	setup_usb_host0(&usb0_board_data);
+}

static void configure_sdhci(void)
 {
@@ -65,6 +79,7 @@
    if (CONFIG(HEROBRINE_HAS_FINGERPRINT))
    	gpio_output(GPIO_FP_RST_L, 1);

+	setup_usb();
 }

static void mainboard_enable(struct device *dev)
diff --git a/src/mainboard/google/herobrine/romstage.c b/src/mainboard/google/herobrine/romstage.c
index ad2d2a0..2ea78b8 100644
--- a/src/mainboard/google/herobrine/romstage.c
+++ b/src/mainboard/google/herobrine/romstage.c
@@ -1,16 +1,26 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/stages.h>
+#include <soc/usb/usb_common.h>
 #include <soc/qclib_common.h>
 #include "board.h"
 #include <soc/shrm.h>

+static void prepare_usb(void)
+{
+	/*
+	* Do DWC3 core and phy reset. Kick these resets
+	* off early so they get at least 1ms to settle.
+	*/
+	reset_usb0();
+}
+
 void platform_romstage_main(void)
 {
    shrm_fw_load_reset();
    /* QCLib: DDR init & train */
    qclib_load_and_run();
-
+	prepare_usb();
    /* This rail needs to be stable by the time we take the FPMCU out of
       reset in ramstage, so already turn it on here. This needs to happen
       at least 200ms after this pin was first driven low in the bootblock. */